• Title/Summary/Keyword: floating-point

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Implementation of the High-Quality Audio System with the Separately Processed Musical Instrument Channels (악기별 분리처리를 통한 고음질 오디오 시스템 구현)

  • Kim, Tae-Hoon;Lee, Sang-Hak;Kim, Dae-Kyung;Lee, Sang-Chan
    • The Journal of the Acoustical Society of Korea
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    • v.32 no.4
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    • pp.346-353
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    • 2013
  • This paper deals with the implementation of a high-quality audio system for karaoke. For improving the key/tempo changes performance, we separated the audio into many musical instrument channels. By separating musical instrument channels, high-quality key/tempo changes can be achieved and we confirmed this using the cross-correlation distribution and the MOS evaluation. The improved audio system was implemented using the TMS320C6747 DSP with fixed/floating-point operations. The implemented audio system can perform the multi-channel WMA decoding, the MP3 encoding/decoding, the wav playing, the EQ, and the key/tempo changes in real time. The WMA channels used for processing the separated instrument channels. The audio system includs the MP3 encoding/decoding function for playing and recording and the wav channel for the effect sound.

A Study on the Development of Dynamic Positioning System for Barge Type Surface Vessels (Barge 형 수상선의 DP(Dynamic Positioning) System 개발에 관한 연구)

  • Bui, Van-Phuoc;Kim, Young-Bok
    • Journal of Power System Engineering
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    • v.16 no.2
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    • pp.66-74
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    • 2012
  • In this paper, the authors propose a new approach to control a barge type surface vessel. It is based on the Dynamic Positioning System(DPS) design. The main role of barge ship is to carry and supply the materials to the floating units and other places. To carry out this job, it should be positioned in the specified area. However sometimes the thrust systems are installed on it, and in general the rope control by mooring winch system is used. It may be difficult to compare the control performances of two types. If we consider this problem in point of usefulness, we can easily find out that the winch control system is more useful and applicable to the real field than the thrust control system except a special use. Therefore, in this paper we consider a DPS design problem which can be extended to the many application fields. The goal of this paper is twofold. First, the sliding mode controller (SMC) for positioning the our vessel is proposed. Especially, in this paper, a robust stability condition is given based on descriptor system representation. In the result, the sliding mode control law guarantees to keep the vessel in the defined area in the presence of environmental disturbances. And second, the thrust allocation problem is solved by using redistributed pseudo-inverse (RPI) algorithm to determine the thrust force and direction of each individual actuator. The proposed approach has been simulated with a supply vessel model and found work well.

Development of Power Management System for Efficient Energy Usage of Small Generator (소형 발전기의 에너지 절약을 위한 전력관리 시스템 개발)

  • Jeon, Min-Ho;Oh, Chang-Hyun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.12
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    • pp.2601-2606
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    • 2012
  • In this paper, an electricity management system, which saves energy by utilizing electricity consumption of load from an environment that uses at least two compact generators, is proposed and developed. A hardware is constructed by using TMS320C6713 DSP chip made by TI that is capable of high speed hardware floating point processing while serial communication is used for communication with a monitoring PC. Manual control is made possible from the monitoring PC and automatic on/off is enabled in the generator by using data collected by CT/PT sensor from the DSP mainboard. Test results confirm that the electricity management system proposed in this study functions without abnormality. The application of an algorithm that saves energy by using electricity consumption of load also allows for a longer supply of electricity compared to continuously using two compact generators.

Modified Electrical Resistivity Survey for Leakage Detection of a Waterside Concrete Barrage (콘크리트 수변구조물의 누수 탐지를 위한 변형된 전기비저항 탐사 연구)

  • Lee, Bomi;Oh, Seokhoon;Im, Eunsang
    • Geophysics and Geophysical Exploration
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    • v.18 no.3
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    • pp.115-124
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    • 2015
  • A modified electrical resistivity survey has been suggested and applied to a leakage detection problem of concrete barrage. We suggest the modified electrical resistivity methods using electrodes floating on the water and apply line current sources instead of conventional point current sources in order to facilitate simple analysis. In addition, the study introduced the following three variations of modified electrode array: Direct potential array, Parallel potential array and Cross potential array. These arrays were tested and investigated through numerical experiment, physical model experiment and geophysical field exploration in order to verify their applicability to the water leakage detection of a concrete barrage. When water leakage occurred, all kind of array operations demonstrated distinct changes of aspects of potential difference in graphs obtained by not only the numerical and physical model experiments but also geophysical field exploration. Therefore, this modified electrode arrays of electrical resistivity survey, which has been adapted to the concrete barrage, has been found to be a useful method to detect water leakage.

A Design of Hybrid Lossless Audio Coder (Hybrid 무손실 오디오 부호화기의 설계)

  • 박세형;신재호
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.41 no.6
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    • pp.253-260
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    • 2004
  • This paper proposes a novel algorithm for hybrid lossless audio coding, which employs an integer wavelet transform and a linear prediction model. The proposed algorithm divides the input signal into flames of a proper length, decorrelates the framed data using the integer wavelet transform and linear prediction and finally entropy-codes the frame data. In particular, the adaptive Golomb-Rice coding method used for the entropy coding selects an optimal option which gives the best compression efficiency. Since the proposed algorithm uses integer operations, it significantly improves the computation speed in comparison with an algorithm using real or floating-point operations. When the coding algorithm is implemented in hardware, the system complexity as well as the power consumption is remarkably reduced. Finally, because each frame is independently coded and is byte-aligned with respect to the frame header, it is convenient to move, search, and edit the coded, compressed data.

Hardware Design of Special-Purpose Arithmetic Unit for 3-Dimensional Graphics Processor (3차원 그래픽프로세서용 특수 목적 연산장치의 하드웨어 설계)

  • Choi, Byeong-Yoon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.05a
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    • pp.140-142
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    • 2011
  • In this paper, special purpose arithmetic unit for mobile graphics accelerator is designed. The designed processor supports six operations, such as $1/{\chi}$, $\frac{1}{{\sqrt{x}}$, $log_2x$, $2^x$, $sin(x)$, $cos(x)$. The processor adopts 2nd-order polynomial minimax approximation scheme based on IEEE floating point data format to satisfy accuracy conditions and has 5-stage pipeline structure to meet high operational rates. The SFAU processor consists of 23,000 gates and its estimated operating frequency is about 400 Mhz at operating condition of 65nm CMOS technology. Because the processor can execute all operations with 5-stage pipeline scheme, it has about 400 MOPS(million operations per second) execution rate. Thus, it can be applicable to the 3D mobile graphics processors.

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Hardware Design of Arccosine Function for Mobile Vector Graphics Processor (모바일 벡터 그래픽 프로세서용 역코사인 함수의 하드웨어 설계)

  • Choi, Byeong-Yoon;Lee, Jong-Hyoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.4
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    • pp.727-736
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    • 2009
  • In this paper, the $arccos(cos^{-1})$ arithmetic unit for mobile graphics accelerator is designed. The mobile vector graphics applications need tight area, execution time, power dissipation, and accuracy constraints compared to desktop PC applications. The designed processor adopts 2nd-order polynomial approximation scheme based on IEEE floating point data format to satisfy speed and accuracy conditions and reduces area via hardware sharing structure. The arccosine processor consists of 15,280 gates and its estimated operating frequency is about 125Mhz at operating condition of $0.35{\mu}m$ CMOS technology. Because the processor can execute arccosine function within 7 clock cycles, it has about 17 MOPS(million arccos operations per second) execution rate and can be applicable to mobile OpenVG processor. And because of its flexible architecture, it can be applicable to the various transcendental functions such as exponential, trigonometric and logarithmic functions via replacement of ROM and minor hardware modification.

Design of Special Function Unit for Vectorized SIMD Programmable Unified Shader (벡터화된 SIMD 프로그램어블 통합 셰이더를 위한 특수 함수 유닛 설계)

  • Jung, Jin-Ha;Kim, Kyeong-Seob;Yun, Jeong-Hee;Seo, Jang-Won;Choi, Sang-Bang
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.5
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    • pp.56-70
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    • 2010
  • Rendering technique generating 2 dimensional image to give reality and high performance graphical processor for efficient processing of massive data are necessary to support realistic 3 dimensional graphical image. Recently, graphical hardwares have evolved rapidly. This enables high quality rendering effect that we were unable to process in realtime. Improving shading technique enabled us to render realistic images but still much time is required for this process. Multiple operational units are being integrated in a graphical processor for effective floating point operation using massive data to process almost real looking images. In this paper, we have designed and implemented a special functional unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed special functional unit. Hardware resource usage rate and execution speed are measured implementing directly on FPGA Virtex-4(xc4vlx200).

Study on Chip Design & Implementation of 32 Bit Floating Point Compatible DSP (32비트 부동소수점 호환 DSP의 설계 및 칩 구현에 관한 연구)

  • Woo, Jong-Sik;Seo, Jin-Keun;Lim, Jae-Young;Park, Ju-Sung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.11
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    • pp.74-84
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    • 2000
  • This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.

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Study on Real-Time Digital Filter Design as Function of Scanning Frequency of Focused Electron Beam (집속 전자 빔 장치에서 스캔 주파수에 따른 실시간 디지털 필터 설계에 관한 연구)

  • Kim, Seung-Jae;Oh, Se-Kyu;Yang, Kyung-Sun;Jung, Kwang-Oh;Kim, Dong-Hwan
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.35 no.5
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    • pp.479-485
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    • 2011
  • To acquire images in a thermionic-scanning electron-beam system, a scanning unit is needed to control the electron beam emitted from the tungsten filament source. In scanning the electron beam on the solid surface, the signalto-noise ratio depends on the scanning frequency. We used a digital filter to reduce noise by analyzing the real-time frequency of a secondary electron signal. The noise and the true image signal were well separated. We designed the digital filter via a DSP floating-point operation, and the noise elimination resulted in enhanced image quality in a highresolution mode.