• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.250-253
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• 2000

In this paper, we Implement a new arithmetic computation for MPEG audio data to overcome the limitations of real number processing in the fixed-point arithmetics, such as: overheads in processing time and power consumption. We aims at efficiently dealing with real numbers by extending the fixed-point arithmetic manipulation for floating-point numbers in MPEG audio data, and implementing the DSP libraries to support the manipulation and computation of real numbers with the fixed-point resources.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.91-100
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• 2006

A scheme is proposed for implementing the block LMS algorithm in a block floating point framework that permits processing of data over a wide dynamic range at a processor complexity and coat as low as that of a fixed point processor. The proposed scheme adopts appropriate formats for representing the filter coefficients and the data. Using these and a new upper bound on the step size, update relations for the filter weight mantissas and exponent are developed, taking care so that neither overflow occurs, nor are quantifies which are already very small multiplied directly. It is further shown how the mantissas of the filter coefficients and also the filter output can be evaluated faster by suitably modifying the approach of the fast block LMS algorithm

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.237-242
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• 2017

Along with effluence of non-point pollution source, continuous precipitation due to rainy season or localized heavy rain can also be a good reason for increase of flow rate. And if the water level is going up due to the increase, floating debris around rivers and streams will move because of increased flow velocity. However, currently, there are no studies which perform quantitative calculation on movement of floating debris by analyzing amount of rainfall and flow rate in both domestic and abroad. Thus, the present study calculated amount of movement of floating debris based on moving route monitoring results according to changes of effective rainfall and flow rate that are obtained by using SCS-CN method.

• Journal of the Korea institute for structural maintenance and inspection
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• v.5 no.2
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• pp.183-190
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• 2001

A sub-structure is uplift if the floating greater than dead load of a structure. When such occasion arise, a structure sustain damage. In general, the measures for floating prevention of structure are a permanent anchor method and a drainage method. The primary construction cost of a permanent anchor method is heavy. And a drainage method is needed maintenance management long term. At this point, the measures for floating prevention of a notion being requires the other days. Therefore, at this study a simple construction and a economic vertical drainage system was developed. The findings be used in the in-situ and gave careful consideration to an application. The result of examination, this system considering a characteristic of coefficient of permeability for the ground controls occurrence of floating despite the water level rise of the ground, which a period of construction get shorter compared with other methods, which understood that measures satisfactory in the financial aspect. Especially, A structure occurring effects of flatting under the course of construction made use of it. As the result of the effect of it was confirmed by construction.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.5
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• pp.1157-1162
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• 2015

This paper is the design and implementation to the 4x4 MIMO algorithm based on OFDM, and presented how to verify the implemented result. Algorithm applied the MRVD and QRM-MLD. Matlab and Simulink are used to design channel presumption & MIMO algorithm by Floating-point and Fixed-point model. After then implement VHDL using Modelsim. Performance of algorithm is checked by comparing Simulink model, Modelsim simulation, ISE ChipScope with the result measured by oscilloscope. This method is useful to verify an algorithm with uncompleted system. Conformance between the result of ChipScope and the result of oscilloscope is confirmed, it could be applied on the Backhaul system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1089-1092
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• 1998

Conventional floating-point adders have one data-path that is used for all operations. This paper describes a floatingpoint adder eeveloped for low power consumption, which has three data-paths one of which is selected according to the exponent difference. The first is applied to the case that the absolute exponent difference (AED) of two operands is less than 1, and the second is for 1

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.353-356
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• 2000

In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors and supports all rounding modes defined by IEEE 754 standard, is designed using the series expansion algorithm. This divider shares and fully utilizes the two MAC units for quadratical convergence to the correct quotient. The area increase of two MAC units due to the division is minimized in this design, so that it can be suitable for embedded processors. The tested HDL codes are synthesized and optimized with 0.35$\mu\textrm{m}$ CMOS standard celt libraries. The results show that the latency of the synthesized divider is 17.43 ㎱ in worst condition. But, the divider calculates the correct rounded quotient through only 6 cycles.

• Journal of IKEEE
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• v.11 no.4
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• pp.358-363
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• 2007

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.