Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 1998.10a
- /
- Pages.1089-1092
- /
- 1998
Low Power Architecture for Floating Point Adder
부동소수점 덧셈 연사기의 저전력화 구조
Abstract
Conventional floating-point adders have one data-path that is used for all operations. This paper describes a floatingpoint adder eeveloped for low power consumption, which has three data-paths one of which is selected according to the exponent difference. The first is applied to the case that the absolute exponent difference (AED) of two operands is less than 1, and the second is for 1
Keywords