• Journal of KIISE:Computing Practices and Letters
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• v.14 no.4
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• pp.378-388
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• 2008

Flash memory has been attracting attention as the next mass storage media for mobile computing systems such as notebook computers and UMPC(Ultra Mobile PC)s due to its low power consumption, high shock and vibration resistance, and small size. A storage system with flash memory excels in random read, sequential read, and sequential write. However, it comes short in random write because of flash memory's physical inability to overwrite data, unless first erased. To overcome this shortcoming, we propose an SSD(Solid State Disk) architecture with two novel features. First, we utilize non-volatile FRAM(Ferroelectric RAM) in conjunction with NAND flash memory, and produce a synergy of FRAM's fast access speed and ability to overwrite, and NAND flash memory's low and affordable price. Second, the architecture categorizes host write requests into small random writes and large sequential writes, and processes them with two different buffer management, optimized for each type of write request. This scheme has been implemented into an SSD prototype and evaluated with a standard PC environment benchmark. The result reveals that our architecture outperforms conventional HDD and other commercial SSDs by more than three times in the throughput for random access workloads.

• Journal of Advanced Navigation Technology
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• v.13 no.4
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• pp.509-514
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• 2009

In this paper, we designed and analyzed 256GB DRAM-based SSD storage using DDR1 memory and PCI-e interface. SSD is a storage system that uses DRAM or NAND Flash as primary storage media. Since the SSD read and write data directly to memory chips, which results in storage speeds far greater than conventional magnetic storage devices, HDD. Architecture of the proposed SSD system has performance of high speed data processing duo to use multiple RAM disks as primary storage and PCI-e interface bus as communication path of RAM disks. We constructed experimental system with UNIX, Windows/Linux server, SAN Switch, and Ethernet Switch and measured IOPS and bandwidth of proposed SSD using IOmeter. In experimental results, it has been shown that IOPS, 470,000 and bandwidth,800MB/sec of the DDR-1 SSD is better than those of the HDD and Flash-based SSD.

• Journal of KIISE:Databases
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• v.35 no.5
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• pp.400-410
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• 2008

Flash memory has been widely used in mobile devices, such as mobile phone and digital camera. Recently flash SSD(Solid State Disk), having same interface of the disk drive, is replacing the hard disk of some laptop computers. However, flash memory still cannot be considered as the storage of database systems. The FTL(Flash Translation Layer) of commercial flash SSD, making flash memory operate exactly same as a hard disk, shows poor performance on the workload of databases with many random overwrites. Recently In-Page Logging(IPL) approach was proposed to solve this problem. In this paper, we implement IPL approach on SQLite, a popular open source embedded DBMS, and evaluate its performance. It improves the performance by up to 30 factors for update queries.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.371-375
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• 2010

SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.2
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• pp.27-35
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• 2021

NAND flash memory-based SSD needs an internal software, Flash Translation Layer(FTL) to provide traditional block device interface to the host because of its physical constraints, such as erase-before-write and large erase block. However, because useful host-side information cannot be delivered to FTL through the narrow block device interface, SSDs suffer from a variety of problems such as increasing garbage collection overhead, large tail-latency, and unpredictable I/O latency. Otherwise, the new type of SSD, open-channel SSD exposes the internal structure of SSD to the host so that underlying NAND flash memory can be managed directly by the host-level FTL. Especially, I/O data classification by using host-side information can achieve the reduction of garbage collection overhead. In this paper, we propose a new scheme to reduce garbage collection overhead of open-channel SSD by separating the journal from other file data for the journaling filesystem. Because journal has different lifespan with other file data, the Write Amplification Factor (WAF) caused by garbage collection can be reduced. The proposed scheme is implemented by modifying the host-level FTL of Linux and evaluated with both Fio and Filebench. According to the experiment results, the proposed scheme improves I/O performance by 46%~50% while reducing the WAF of open-channel SSDs by more than 33% compared to the previous one.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.4
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• pp.215-225
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• 2010

The NAND flash memory based SSDs are considered to replace the existing HDDs. To maximize the I/O performance, SSD is composed of several NAND flash memories in parallel. However, to adopt the hybrid mapping scheme in SSD may cause degradation of the I/O performance. In this paper, we propose a new mapping scheme for the SSD called WADPM. WADPM loads only necessary mapping information into RAM and dynamically adjusts the size of mapping information in the RAM. So, WADPM avoids the shortcoming of page-level mapping scheme that requires too large mapping table. Performance evaluation using simulations shows that I/O performance of WADPM is 3.5 times better than the hybrid-mapping scheme and maximum size of mapping table of WADPM is about 50% in comparison with the page-level mapping scheme.

• Journal of the Korea Society of Computer and Information
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• v.26 no.2
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• pp.11-18
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• 2021

The flash translation layer(FTL) of SSD maps the logical page number requested from the host to the actual recorded flash memory page number. It is very important to reduce the amount of RAM used to manage the mapping information. In the existing demand-based FTLs, two-level method is applied in which mapping information is also recorded in flash memory pages and only their addresses are managed as a table in RAM. As the capacities of SSDs are growing to tens of terabytes, the amount of RAM for mapping table becomes too large. In this paper, ML-FTL was proposed as a method of managing mapping information in three levels to reduce the amount of RAM required drastically. From an evaluation, the increase in overhead was minimal compared to the conventional two-level method by properly utilizing cache.

• Journal of Internet of Things and Convergence
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• v.8 no.4
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• pp.9-15
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• 2022

NAND flash memory is used as a medium for various storage devices due to its high data processing speed with low power consumption. However, since the read processing speed of data is about 10 times faster than the write processing speed, various studies are being conducted to improve the speed difference. In particular, flash dedicated buffer management policies have been studied to improve write speed. However, SSD(solid state disks), which has recently been used for various purposes, is more vulnerable to read performance than write performance. In this paper, we find out why read performance is slower than write performance in SSD composed of NAND flash memory and study buffer management policies to improve it. The buffer management policy proposed in this paper proposes a method of improving the speed of a flash-based storage device by analyzing the pattern of read data and applying a policy of pre-reading data to be requested in the future from NAND flash memory. It also proves the effectiveness of the read-ahead policy through simulation.

• Journal of Internet of Things and Convergence
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• v.7 no.4
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• pp.9-14
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• 2021

In computing systems that require high reliability, the method of predicting the lifetime of a storage device is one of the important factors for system management because it can maximize usability as well as data protection. The life of a solid state drive (SSD) that has recently been used as a storage device in several storage systems is linked to the life of the NAND flash memory that constitutes it. Therefore, in a storage system configured using an SSD, a method of accurately and efficiently predicting the lifespan of a NAND flash memory is required. In this paper, a method for optimizing the lifetime prediction of a flash memory-based storage device using the frequency of NAND flash memory failure is proposed. For this, we design a cost matrix to collect the frequency of defects that occur when processing data in units of Drive Writes Per Day (DWPD). In addition, a method of predicting the remaining cost to the slope where the life-long finish occurs using the Gradient Descent method is proposed. Finally, we proved the excellence of the proposed idea when any defect occurs with simulation.

• Journal of KIISE
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• v.43 no.2
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• pp.177-185
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• 2016

In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.