• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.23-31
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• 2011

Recently, Solid state disk is mainly used because this device has lower power consumption as well as higher response time. But it features higher price and lower performance at delete and write operations compared with HDD. To compensate this defect, Hybrid hard disk with internal non-volatile flash memory was issued. This NVCache is used as a kind of cache for disk blocks. In this paper, an I/O scheme for H-HDD is proposed for improving low power consumption as well as response time. Our method is to use this NVCache as read cache mainly and write cache when write requests are concentrated. In read cache operation, disk blocks with higher priority determined on basis of time as well as spatial localities are prefetched, which can improve response time. The write operation is conducted only at write peak time as disk spindle up costs higher battery power as well as response time. Experiments results show that the suggested method can improve response time of H-HDD and lower the power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.493-497
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• 2005

This paper is about the research of the User Agent implementation under wireless embedded environment, using SIP which is one of protocol components construct the VoIP system. The User Agent is made of the User Agent configuration block, the device thread block to control devices and the SIP stack block to process SIP messages. The device thread consists of the RTP thread and the sound lard device processing block. Futhermore, the SIP stack consist of the worker thread to process proxy events, the SIP transceiver and SIP thread to transfer and receive SIP messages. The H/W platform is a board included the Intel's XScale PXA255 processor, flash memory, SDRAM, Audio CODEC module and wireless LAN threough PCMCIA socket, furthermore a microphone and headphone is used by the audio 1/0. The system has embedded linux kernel 2.4.19. For embedded environment, the function of User Agent and SIP method is diminished. Finally, the resource of system could be reduced about $12.9\%$, compared to overall system resource, by minimizing peripherals control and excepting TCP.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• Journal of KIISE
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• v.42 no.2
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• pp.169-176
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• 2015

The atomic write technique is a good solution to solve the problem of the double write buffer. The atomic write technique needs modified I/O subsystems (i.e., file system and I/O schedulers) and a special SSD that guarantees the atomicity of the write request. In this paper, we propose the writing unit aligned block allocation technique (for EXT4 file system) and the merge prevention of requests technique for the CFQ scheduler. We also propose an atomic write-supporting SSD which stores the atomicity information in the spare area of the flash memory page. We evaluate the performance of the proposed atomic write scheme in MariaDB using the tpcc-mysql and SysBench benchmarks. The experimental results show that the proposed atomic write technique shows a performance improvement of 1.4~1.5 times compared to the double write buffer technique.

• KIISE Transactions on Computing Practices
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• v.21 no.1
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• pp.52-57
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• 2015

In this paper, we analyze the performance of the TRIM commands on various SSDs and, based on our analysis results, we enhance the performance of these TRIM commands in the Ext4 file system. We observed that the performance of the TRIM commands improves as the size of the LBA-range increases, the sector number is aligned and continuous or more LBA-ranges are notified via a single TRIM command. However, although the performance is better when multiple LBA-ranges are informed by a single TRIM command, the Ext4 file system issues a single TRIM command for every LBA-range. In this paper, we modify the Ext4 file system to convey at most 64 LBA-ranges per TRIM command. Evaluations through Filebench show that the performance of file deletion operations is improved by up to 35%.

• Journal of the Korea Society of Computer and Information
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• v.17 no.9
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• pp.103-112
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• 2012

Recently, the infrastructure to be connected to the internet is much provided, there is more and more need to connect electric or electronic products to the internet to monitor or control them remotely. However, most of the existing products lack the network interface, so it was very inconvenient to be connected to the internet. Therefore, this article designs and realizes the internet outlet allowing real-time scheduling that can control the power remotely on the internet by using the hardware TCP/IP processor. The realized product consumes low production cost because it can be realized by using the hardware TCP/IP processor and the 8-bit small microprocessor. In addition, the product can be used widely in both wired and wireless environments with a variety of user interface, including the dedicated control program which provides the environment configuration functions; embedded web service that enables the webpage to be saved on the external flash memory; Android smartphone application; motion recognition control environment that uses the OpenCV computer vision library, etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.77-83
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• 2004

In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.

• Korean Chemical Engineering Research
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• v.46 no.1
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• pp.1-6
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• 2008

Block copolymers spontaneously assemble into various nanoscale structures such as spheres, cylinders, and lamellar structures according to the relative volumn ratio of each macromolecular block and their overall molecular weights. The self-assembled structures of block copolymer have been extensively investigated for the applications such as nanocomposites, photonic crystals, nanowires, magnetic-storage media, flash memory devices. However, the naturally formed nanostructures of block copolymers contain a high density of defects such that the practical applications for nanoscale devices have been limited. For the practical application of block copolymer nanostructures, a robust process to direct the assembly of block copolymers in thin film geometry is required to be established. To exploit self-assembly of block copolymer for the nanotechnology, it is indispensible to fabricate defect-free self-assembled nanostructure over an arbitrarily large area.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5B
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• pp.386-394
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• 2008

Adoption of wireless communication facilities in mobile devices leads to increased vulnerability in individual privacy. One of such cases was discovered when a smart mobile phone of Paris Hilton at Oscar Award Ceremony was hacked a Swedish group of hackers. In this study, I wondered what sort of personal information could be exposed to hackers in such cases. In the course of survey, it was recognized that technical analysis of flash memory in mobile devices to check what kinds of data are stored there is technically almost impossible, since they are usually built in a proprietary manner. No generic tools could apply to discover their contents. Having recognized technical difficulties, it was inevitable to resort to a questionnaire survey to see awareness level with regard to personal privacy. We collected response from three hundred respondents by posting the questionnaire at World Survey on-line research site. What we have discovered was quite astonishing that even personal residence registration numbers have been found from nine of every ten respondents. Other data revealed include phone numbers, names, and personal bank accounts.