• ETRI Journal
• /
• v.45 no.4
• /
• pp.690-703
• /
• 2023

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 ㎛. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 ㎼.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.6
• /
• pp.768-776
• /
• 2014

Using a simplified high-frequency small-signal equivalent circuit model for BSIM3 MOSFET, the fully differential two-stage folded-cascode CMOS operational amplifier is analyzed to obtain its small-signal voltage transfer function. As a result, the expressions for dc gain, five zero frequencies, five pole frequencies, unity-gain frequency, and phase margin are derived for op amp design using design equations. Then the analysis result is verified through the comparison with Spice simulations of both a high speed op amp and a low power op amp designed for the $0.13{\mu}m$ CMOS process.

• Proceedings of the IEEK Conference
• /
• 2000.06e
• /
• pp.191-194
• /
• 2000

A 2.4 GHz single ended two stage low noise amplifier(LNA) is designed for Bluetooth application. The circuit was implemented in a standard digital 0.25 $\mu\textrm{m}$ CMOS process with one poly and five metal layers. At 2.4 GHz, the LNA dissipates 34.5 mW from a 2.5V power supply voltage and provides 24.6 dB power gain, 2.85 dB minimum noise figure, -66.3 dB reverse isolation, and an output 1-dB compression level of 8.5 dBm.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.36 no.10
• /
• pp.741-747
• /
• 1987

The high-power Nd:glass system with five-stage amplifier was designed and its amplification characteristics was studied for developing high-power Nd:glass laser system as an energy driver of inertial confinement fusion(ICF). In order to study the amplification characteristics of remporal and spacial Gaussian laser beam, the dependence of them on pumping efficiency and rod loss were studied and discussed. The output energy of this system using phosphate Nd glass rod(LHG-7,LHG-8) and silicate Nd glass rod(LSG-91H), respectively, was calculated by the computer simulation using Avizonis-Grotbeck and Frantz Nodvik equations. As results of this simulation, it was found that the shorter the risetime of laser pulse, the larger the amplification factor and that the larger peak value of laser pulse, the lower the amplification factor. The output inergies of 179J, 344J, and 7J were obtained by the designed five-stage amplified high-power Nd:glass laser system using glass rods of LHG-7,LHG-8, and LSG-91H, respectively. From the results it was found that the laser system using the LHG-8 glass rod was the most excellent one among the systems and the cross section for stimulated emission of the gain coefficient was essentially important parameter for the amplification characteristics.

• ETRI Journal
• /
• v.34 no.4
• /
• pp.485-491
• /
• 2012

In this paper, the implementations of a $0.1{\mu}m$ gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process for a low noise amplifier (LNA), a subharmonically pumped (SHP) mixer, and a single-chip receiver for 70/80 GHz point-to-point communications are presented. To obtain high-gain performance and good flatness for a 15 GHz (71 GHz to 86 GHz) wideband LNA, a five-stage input/output port transmission line matching method is used. To decrease the package loss and cost, 2nd and 4th SHP mixers were designed. From the measured results, the five-stage LNA shows a gain of 23 dB and a noise figure of 4.5 dB. The 2nd and 4th SHP mixers show conversion losses of 12 dB and 17 dB and input P1dB of -1.5 dBm to 1.5 dBm. Finally, a single-chip receiver based on the 4th SHP mixer shows a gain of 6 dB, a noise figure of 6 dB, and an input P1dB of -21 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.22-26
• /
• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.