• Title/Summary/Keyword: field effect transistor

Search Result 795, Processing Time 0.031 seconds

Three-Dimensional Selective Oxidation Fin Channel MOSFET Based on Bulk Silicon Wafer (벌크 실리콘 기판을 이용한 삼차원 선택적 산화 방식의 핀 채널 MOSFET)

  • Cho, Young-Kyun;Nam, Jae-Won
    • Journal of Convergence for Information Technology
    • /
    • v.11 no.11
    • /
    • pp.159-165
    • /
    • 2021
  • A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.

Development of Portable Measurement Unit with Wireless Transmission by Wireless LAN for Long-term Monitoring (장기간 소자 모니터링이 용이한 소형 무선랜 무선송신 계측장치 개발)

  • Park, So Jeong;Park, Il-Hoo;Moon, Young-Sun;Lee, Kook Jin;Kim, Gyu-Tae
    • Journal of the Semiconductor & Display Technology
    • /
    • v.17 no.1
    • /
    • pp.45-49
    • /
    • 2018
  • Portable microcontroller based measurement unit is demonstrated using digital-to-analog convertor module, analog-to-digital convertor module and additional preamplifier circuit with low-budget but excellent performances. Using the designed measurement unit, the measurement of current below 1 nA with applying voltage up to 5 V is successfully carried out. With the WiFi module in microcontroller, measured data is transferred to the user's computer. To evaluate the performance of the measurement unit, the transfer curve of a commercial N-type field effect transistor was measured with the measurement unit and the results is well consistent with that measured using commercial characterization system.

CMOS Binary Image Sensor with Gate/Body-Tied PMOSFET-Type Photodetector for Low-Power and Low-Noise Operation

  • Lee, Junwoo;Choi, Byoung-Soo;Seong, Donghyun;Lee, Jewon;Kim, Sang-Hwan;Lee, Jimin;Shin, Jang-Kyoo;Choi, Pyung
    • Journal of Sensor Science and Technology
    • /
    • v.27 no.6
    • /
    • pp.362-367
    • /
    • 2018
  • A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

Optimal Design of GaN-FET based High Efficiency and High Power Density Boundary Conduction Mode Active Clamp Flyback Converter (GaN-FET 기반의 고효율 및 고전력밀도 경계전류모드 능동 클램프 플라이백 컨버터 최적설계)

  • Lee, Chang-Min;Gu, Hyun-Su;Ji, Sang-Keun;Ryu, Dong-Kyun;Kang, Jeong-Il;Han, Sang-Kyoo
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.24 no.4
    • /
    • pp.259-267
    • /
    • 2019
  • An active clamp flyback (ACF) converter applies a clamp circuit and circulates the energy of leakage inductance to the input side, thereby achieving a zero-voltage switching (ZVS) operation and greatly reducing switching losses. The switching losses are further reduced by applying a gallium nitride field effect transistor (GaN-FET) with excellent switching characteristics, and ZVS operation can be accomplished under light load with boundary conduction mode (BCM) operation. Optimal design is performed on the basis of loss analysis by selecting magnetization inductance based on BCM operation and a clamp capacitor for loss reduction. Therefore, the size of the reactive element can be reduced through high-frequency operation, and a high-efficiency and high-power-density converter can be achieved. This study proposes an optimal design for a high-efficiency and high-power-density BCM ACF converter based on GaN-FETs and verifies it through experimental results of a 65 W-rated prototype.

Design and Analysis of Universal Power Converter for Hybrid Solar and Thermoelectric Generators

  • Sathiyanathan, M.;Jaganathan, S.;Josephine, R.L.
    • Journal of Power Electronics
    • /
    • v.19 no.1
    • /
    • pp.220-233
    • /
    • 2019
  • This work aims to study and analyze the various operating modes of universal power converter which is powered by solar and thermoelectric generators. The proposed converter is operated in a DC-DC (buck or boost mode) and DC-AC (single phase) inverter with high efficiency. DC power sources, such as solar photovoltaic (SPV) panels, thermoelectric generators (TEGs), and Li-ion battery, are selected as input to the proposed converter according to the nominal output voltage available/generated by these sources. The mode of selection and output power regulation are achieved via control of the metal-oxide semiconductor field-effect transistor (MOSFET) switches in the converter through the modified stepped perturb and observe (MSPO) algorithm. The MSPO duty cycle control algorithm effectively converts the unregulated DC power from the SPV/TEG into regulated DC for storing energy in a Li-ion battery or directly driving a DC load. In this work, the proposed power sources and converter are mathematically modelled using the Scilab-Xcos Simulink tool. The hardware prototype is designed for 200 W rating with a dsPIC30F4011 digital controller. The various output parameters, such as voltage ripple, current ripple, switching losses, and converter efficiency, are analyzed, and the proposed converter with a control circuit operates the converter closely at 97% efficiency.

2500 fps High-Speed Binary CMOS Image Sensor Using Gate/Body-Tied Type High-Sensitivity Photodetector (Gate/Body-Tied 구조의 고감도 광검출기를 이용한 2500 fps 고속 바이너리 CMOS 이미지센서)

  • Kim, Sang-Hwan;Kwen, Hyeunwoo;Jang, Juneyoung;Kim, Young-Mo;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
    • /
    • v.30 no.1
    • /
    • pp.61-65
    • /
    • 2021
  • In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a high-speed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.

Development of Selective GaN etching Process for p-GaN/AlGaN/GaN E-mode FET Fabrication (p-GaN/AlGaN/GaN E-mode FET 제작을 위한 선택적 GaN 식각 공정 개발)

  • Jang, Won-Ho;Cha, Ho-Young
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.24 no.2
    • /
    • pp.321-324
    • /
    • 2020
  • In this work, we developed a selective etching process for GaN that is a key process in p-GaN/AlGaN/GaN enhancement-mode (E-mode) power switching field-effect transistor (FET) fabrication. In order to achieve a high current density of p-GaN/AlGaN/GaN E-mode FET, the p-GaN layer beside the gate region must be selectively etched whereas the underneath AlGaN layer should be maintained. A selective etching process was implemented by oxidizing the surface of the AlGaN layer and the GaN layer by adding O2 gas to Cl2/N2 gas which is generally used for GaN etching. A selective etching process was optimized using Cl2/N2/O2 gas mixture and a high selectivity of 53:1 (= GaN/AlGaN) was achieved.

Device modelling and performance analysis of two-dimensional AlSi3 ballistic nanotransistor

  • Chuan, M.W.;Wong, K.L.;Hamzah, A.;Rusli, S.;Alias, N.E.;Lim, C.S.;Tan, M.L.P.
    • Advances in nano research
    • /
    • v.10 no.1
    • /
    • pp.91-99
    • /
    • 2021
  • Silicene is an emerging two-dimensional (2D) semiconductor material which has been envisaged to be compatible with conventional silicon technology. This paper presents a theoretical study of uniformly doped silicene with aluminium (AlSi3) Field-Effect Transistor (FET) along with the benchmark of device performance metrics with other 2D materials. The simulations are carried out by employing nearest neighbour tight-binding approach and top-of-the-barrier ballistic nanotransistor model. Further investigations on the effects of the operating temperature and oxide thickness to the device performance metrics of AlSi3 FET are also discussed. The simulation results demonstrate that the proposed AlSi3 FET can achieve on-to-off current ratio up to the order of seven and subthreshold swing of 67.6 mV/dec within the ballistic performance limit at room temperature. The simulation results of AlSi3 FET are benchmarked with FETs based on other competitive 2D materials such as silicene, graphene, phosphorene and molybdenum disulphide.

Fabrication of the FET-based SPM probe by CMOS standard process and its performance evaluation (CMOS 표준 공정을 통한 SPM 프로브의 제작 및 그 성능 평가)

  • Lee, Hoontaek;Kim, Junsoo;Shin, Kumjae;Moon, Wonkyu
    • Journal of Sensor Science and Technology
    • /
    • v.30 no.4
    • /
    • pp.236-242
    • /
    • 2021
  • In this paper, we report the fabrication of the tip-on-gate of a field-effect-transistor (ToGoFET) probe using a standard complementary metal-oxide-semiconductor (CMOS) process and the performance evaluation of the fabricated probe. After the CMOS process, I-V characteristic measurement was performed on the reference MOSFET. We confirmed that the ToGoFET probe could be operated at a gate voltage of 0 V due to channel ion implantation. The transconductance at the operating point (Vg = 0 V, Vd = 2 V) was 360 ㎂/V. After the fabrication process was completed, calibration was performed using a pure metal sample. For sensitivity calibration, the relationship between the input voltage of the sample and the output current of the probe was determined and the result was consistent with the measurement result of the reference MOSFET. An oxide sample measurement was performed as an example of an application of the new ToGoFET probe. According to the measurement, the ToGoFET probe could spatially resolve a hundred nanometers with a height of a few nanometers in both the topographic image and the ToGoFET image.

Highly-Sensitive Gate/Body-Tied MOSFET-Type Photodetector Using Multi-Finger Structure

  • Jang, Juneyoung;Choi, Pyung;Kim, Hyeon-June;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
    • /
    • v.31 no.3
    • /
    • pp.151-155
    • /
    • 2022
  • In this paper, we present a highly-sensitive gate/body-tied (GBT) metal-oxide semiconductor field-effect transistor (MOSFET)-type photodetector using multi-finger structure whose photocurrent increases in proportion to the number of fingers. The drain current that flows through a MOSFET using multi-finger structure is proportional to the number of fingers. This study intends to confirm that the photocurrent of a GBT MOSFET-type photodetector that uses the proposed multi-finger structure is larger than the photocurrent per unit area of the existing GBT MOSFET-type photodetectors. Analysis and measurement of a GBT MOSFET-type photodetector that utilizes a multi-finger structure confirmed that photocurrent increases in ratio to the number of fingers. In addition, the characteristics of the photocurrent in relation to the optical power were measured. In order to determine the influence of the incident the wavelength of light, the photocurrent was recorded as the incident the wavelength of light varied over a range of 405 to 980 nm. A highly-sensitive GBT MOSFET-type photodetector with multi-finger structure was designed and fabricated by using the Taiwan semiconductor manufacturing company (TSMC) complementary metal-oxide-semiconductor (CMOS) 0.18 um 1-poly 6-metal process and its characteristics have been measured.