• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.5
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.4
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• pp.218-221
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].

• ETRI Journal
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• v.35 no.4
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• pp.734-737
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• 2013

Nonvolatile ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) memory based on an organic thin-film transistor with inkjet-printed dodecyl-substituted thienylenevinylene-thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of -12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 $cm^2/Vs$, $10^5$, and $10^{-10}$ A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.28-33
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• 1985

ISFETS for physiological applications have been developed using the techniques for integrated circuit fabrication. The silicon nitride layer was used as a H+ sensing membrane. However, K+, Na+ and Ca++ sensing ISFETS were fabricated by forming tach specification sensing membranes over the silicon nitride gate insulator. The sensitivities of the fabricated devices were very good. The typical values of measured sentivities were iEmV/pH, 42mv1, pH,5 gmV/pNa and 28mv1p0a. However, the selectivity and stability should be somewhat improved for practical physiological uses with good reliability. The response times were, less than one second, short enough for the practical uses in physiological applications.

• Bulletin of the Korean Chemical Society
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• v.33 no.4
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• pp.1213-1219
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• 2012

The reorganization energy and the spectroscopic properties of 2,6-bis(5'-hexyl-thieno[3,2-b]thiophene-2'- yl)naphthalene (DH-TNT) and 2,6-bis(5'-hexyl-thieno[3,2-b]thiophene-2'-yl)anthracene (DH-TAT), which are composed of an acene unit and alkylated thienothiophene on both sides, as organic materials for display devices were calculated and the results were compared with experimental values. The lower reorganization energy of the DH-TAT over the DH-TNT calculated by the density functional theory is attributed to a smaller vibrational distortion because of the heavier building block of DH-TAT, and it shows a good field effect performance over the DH-TNT. The calculated spectra and the other spectroscopic characteristic of the compounds are well consistent with those of observed results.

• Bulletin of the Korean Chemical Society
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• v.28 no.11
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• pp.2056-2060
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• 2007

A successful combination of “oxygen-assisted chemical vapor deposition (CVD) process” and Co catalyst nanoparticles to grow highly pure single walled carbon nanotubes (SWNTs) was demonstrated. Recently, it was reported that addition of small amounts of oxygen during CVD process dramatically increased the purity and yield of carbon nanotubes. However, this strategy could not be applied for discrete Fe nanoparticle catalysts from which appropriate yields of SWNTs could be grown directly on solid substrates, and fabricated into field effect transistors (FETs) quite efficiently. The main reason for this failure is due to the carbothermal reduction which results in SiO2 nanotrench formation. We found that the oxygen-assisted CVD process could be successfully applied for the growth of highly pure SWNTs by switching the catalyst from Fe to Co nanoparticles. The topological morphologies and p-type transistor electrical transport properties of the grown SWNTs were examined by using atomic force microscope (AFM), Raman, and from FET devices fabricated by photolithography.

• Bulletin of the Korean Chemical Society
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• v.34 no.5
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• pp.1355-1360
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• 2013

We have developed a new multifunctional material, 4,4',4"-tris(4-naphthalen-2-yl-phenyl)amine (2-TNPA), which can be used as a blue-emitting and hole-transporting material in organic light-emitting diodes (OLEDs), as well as a donor material in organic solar cells (OSCs) and an active material in organic thin-film transistors (OTFTs). The OLED device doped with 3% 2-TNPA shows a maximum current efficiency of 3.0 $cdA^{-1}$ and an external quantum efficiency of 3.0%. 2-TNPA is a more efficient hole-transporting material than 4,4'-bis[N-(naphthyl-N-phenylamino)]biphenyl (NPD). Furthermore, 2-TNPA shows a power-conversion efficiency of 0.39% in OSC and a field-effect mobility of $3.2{\times}10^{-4}cm^2V^{-1}s^{-1}$ in OTFTs.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.20.2-20.2
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• 2009

최근 무전해 식각법을 이용한 실리콘 나노와이어 합성이 다양한 각도에서 이루어지고 있다. 무전해 식각법을 통한 나노와이어 합성은, 단결정 실리콘 기판에 촉매를 올려 기판을 식각할 수 있는데, 이 방법을 이용하여 넓은 면적의 수직방향으로 배열된 10 ~ 300nm 지름의 단결정 실리콘 나노와이어를 합성할 수 있다. 본 연구에서는 무전해 식각법으로 boron이 도핑된 p-type실리콘 기판을 식각하여 실리콘 나노와이어를 합성하였고, 단일 나노와이어의 field-effect transistor(FET) 소자가 가지는 전기적 특성에 대하여 분석하였다. 특히 무전해 식각법을 이용하여 나노와이어를 합성할 때, 촉매로 사용되는 Ag particle이 나노와이어에 미치는 영향에 대해서 분석해 보았다. FET 소자의 게이트 절연막은 가장 일반적으로 사용되는 SiO2 (300nm)와 고유전체로 잘 알려진HfO2(80nm)를 사용하여 전기적 특성을 비교하여 보았다. 한편, HfO2 박막은 atomiclayer deposition(ALD)장비를 이용하여 증착하였다. 합성된 실리콘 나노와이어의 경우 X-ray diffraction(XRD)로 결정성을 확인하였으며, high-resolution transmission electron microscopy(HRTEM)으로 결정성 및 나노와이어의 표면 형태를 확인하였다. 전기적 특성은 I-V 측정을 통하여 Ion/Ioff ratio, 이동도, subthreshold swing, subthreshold voltage값을 평가하였다.

• Journal of Information Display
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• v.12 no.1
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• pp.47-50
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• 2011

Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.