• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.403-405
• /
• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.166-173
• /
• 2001

Hysteresis loops of the ferroelectric thin films such as PLZT(10/30/70), PLT(10) and PZT(30/70) was simulated using the field-dependent polarization model and compared to the measured loops. In case of PZT(30/70) thin film, as the real saturation or polarization at the applied voltage or larger than 5V appears slack and its value is quite different from the simulated one, it is deduced that the ferroelectric polarization of PZT(30/70) is generated not only by the pure dipoles but also by various electric charges. The drain current of quasi-MFISFET is expressed by using the square-law FET and field-dependent polarization models. The modeling results are analogous to the experimental values. The channel of quasi-MFISFET using PZT(30/70) forms more quickly compared to that of quasi-MFISFET using PLZT(10/30/70) or PLT(10) in the state of 'write' gate voltage of -10V. This may be because the decrease rate of the polarization in the PZT(30/70) thin film is 3~4 times more rapid than that of the polarization in the PLZT(10/30/70) or the PLT(10) thin film in the retention characteristics.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.277.2-277.2
• /
• 2014

For next-generation electronic applications, human-machine interface devices have recently been demonstrated such as the wearable computer as well as the electronic skin (e-skin). For integration of those systems, it is essential to develop many kinds of components including displays, energy generators and sensors. In particular, flexible sensing devices to detect some stimuli like strain, pressure, light, temperature, gase and humidity have been investigated for last few decades. Among many condidates, a pressure sensing device based on organic field-effect transistors (OFETs) is one of interesting structure in flexible touch displays, bio-monitoring and e-skin because of their flexibility. In this study, we have investigated a flexible e-skin based on highly sensitive, pressure-responsive OFETs using microstructured ferroelectric gate dielectrics, which simulates both rapidly adapting (RA) and slowly adatping (SA) mechanoreceptors in human skin. In SA-type static pressure, furthermore, we also demonstrate that the FET array can detect thermal stimuli for thermoreception through decoupling of the input signals from simultaneously applied pressure. The microstructured highly crystalline poly(vinylidene fluoride-trifluoroethylene) possessing piezoelectric-pyroelectric properties in OFETs allowed monitoring RA- and SA-mode responses in dyanamic and static pressurizing conditions, which enables to apply the e-skin to bio-monitoring of human and robotics.

• ETRI Journal
• /
• v.20 no.2
• /
• pp.241-249
• /
• 1998

The structure and electrical characteristics of metal-ferroelectric-semiconductor FET(MFSFET) for a single transistor memory are presented. The MFSFET was comprised of polysilicon islands as source/drain electrodes and $BaMgF_4$ film as a gate dielectric. The polysilicon source and drain were built-up prior to the formation of the ferroelectric film to suppress a degradation of the film due to high thermal cycles. From the MFS capacitor, the remnant polarization and coercive field were measured to be about $0.6{\mu}C/cm^2$ and 100 kV/cm, respectively. The fabricated MFSFETs also showed good hysteretic I-V curves, while the current levels disperse probably due to film cracking or bad adhesion between the film and the Al electrode.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.9
• /
• pp.1717-1723
• /
• 2007

In this study , quasi-MFISFET (Metal-Ferroelectric-Insulator-Semiconductor FET) devices are fabricated using PLZT(10/30/70), PLT(10), PZT(30/70) thin film and their drain current properties are investigated. It is found that the drain current of quasi-MFISFET is directly influenced by the polarization strength of ferroelectric thin fan. Also, when the gate voltages are ${\pm}5\;and\;{\pm}10V$, the memory windows are 0.5 and 1.3V, respectively. It means that the memory window is changed with the variation of coercive voltage generated by the voltage applied on ferroelectric thin film. The electric field and the leakage current with time delay of PLZT(10/30/70) thin lam are measured to investigate the retention property of MFISFET device. Some material parameters such as current density constant, $J_{ETO}$, electric field dependent factor K and time dependent factor m are obtained. The variation of charge density with time is quantitatively analyzed by using the material parameters.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.55-58
• /
• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.06a
• /
• pp.63-66
• /
• 1998

Prototype MFSFET′s using ferroelectric oxide LiNbO$_3$ as a gate insulator have been successfully fabricated with the help of 2 sheets of metal masks and demonstrated nonvolatile memory operations of the MFSFET′s. The estimated field-effect electron mobility and transconductance on a linear region of the fabricated FET were 600 $\textrm{cm}^2$/V.s and 0.16 mS/mm, respectively. The drain current of the "on" state was more than 4 orders of magnitude larger than the "off" state current at the same "read" gate voltage of 0.5 V, which means the memory operation of the MFSFET. A write voltage as low as $\pm$3 V, which is applicable to low power integrate circuits, was used for polarization reversal.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.7
• /
• pp.83-89
• /
• 1989

Ferroelectric $PbTiO_3$ thin film is deposited with rf sputtering at substrate temperature of $100-150^{\circ}C$. It is found that this has pyrochlore structure of amorphous type by X-ray diffractive analysis. Thermal annealing has excellent characteristics at $550^{\circ}C$ and laser annealing has best crystalline structure in case of scanning with 50 watts. Interface states in MFST and MFOST structure with a $PbTiO_3$ ferroelectric thin film gate have been investigated from analysis of C-V data. The interface states density has been drastically reduced by inserting an oxide layer between ferroelectric and semiconductor. The observed effect increase feasibility of employing ferroelectric thin films such as nonvolatile memory field effect transistor, IR optical FET, and Image Devices with a ferroelectric layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.171-172
• /
• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.1 s.34
• /
• pp.21-26
• /
• 2005

The field effect transistors (FETs) were fabricated ell $Y_2O_3/Si(100)$ substrates by the conventional memory processes and sol-gel process using $(Bi,La)Ti_3O_{12}(BLT)$ ferroelectric gate materials. The remnant polarization ($2Pr = Pr^+-Pr^-$) int Pt/BLT/Pt/Si capacitors increased from $22 {\mu}C/cm^2$ to $30{\mu}C/ cm^2$ at 5V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. There was no drastic degradation in the polarization values after applying the retention read pulse for $10^{5.5}$ seconds. The capacitance-voltage data of $Pt/BLT/Y_2O_3/Si$ capacitors at 5V input voltage showed that the memory window voltage decreased from 1.4V to 0.6V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. The leakage current of the $Pt/BLT/Y_2O_3/Si$ capacitors annealed at $750^{\circ}C$ was about $510^{-8}A/cm^2$ at 5V. From the drain currents versus gate voltages ($V_G$) for $Pt/BLT/Y_2O_3/Si(100)$ FET devices, the memory window voltages increased from 0.3V to 0.8V with increasing tile $V_G$ from 3V to 5V.