• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.1-14
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• 2001

Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.213-225
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• 2002

Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

• 한국진공학회지
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• 제11권2호
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• pp.103-107
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• 2002

Metal/ferroelectric/semiconductor field effect transistors(MFSFET′s) with various gate electrodes, that are aluminum, platinum and poly-Si, using rapid thermal annealed $LiNbO_3$/Si(100) structures were fabricated and the properties of the FET′s have been discussed. The drain current of the "on" state of FET with Pt electrode was more than 3 orders of magnitude larger than the "off" state current at the same "read" gate voltage of 1.5 V, which means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about $10^3$ s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• 대한전자공학회논문지SD
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• 제40권1호
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• pp.1-10
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• 2003

본 연구에서는 Metal-Ferroelecric-Semiconductor FET (MFSFET) 소자의 특성을 시뮬레이션 하였다. 시뮬레이션에서는 field-dependent polarization 모델과 square-law FET 모델이 도입되었다. MFSFET 시뮬레이전에서 C-V/sub G/ 곡선은 축적과 공핍 및 반전 영역을 확실하게 나타내었다. 게이트 전압에 따른 캐패시턴스, subthreshold 전류 그리고, 드레인 전류특성에서 강유전체 항전압이 0.5, 1V 일 때, 각각 1, 2V 의 memory window 를 나타내었다. 드레인 전류-드레인 전압 곡선은 증가영역과 포화영역으로 구성되었다. 드레인 전류-드레인 전압 곡선에서 두 부분의 문턱전압에 의해 나타난 포화드레인 전류차이는 게이트 전압이 0, 0.1, 0.2 그리고, 0.3V 일 때, 각각 1.5, 2.7, 4.0 그리고 5.7㎃ 이었다. 시간경과 후의 드레인 전류를 분석하였는데, PLZT(10/30/70) 박막은 10년 후에 약 18%의 포화 전류가 감소하여 우수한 신뢰성을 보였다. 본 모델은 MFSFET 소자의 동작을 예측하는데 중요한 역할을 할 것으로 판단된다.

• 한국정보통신학회논문지
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• 제11권3호
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• pp.570-576
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• 2007

본 연구에서는 field-dependent polarization 모델과 square-law FET 모델을 이용하여 Metal- ferroelectic-semiconductor FET (MFSFET) 소자의 특성을 연구하였다. 게이트 전압에 따른 드레인 전류특성에서 강유전체 박막의 항전압이 0.5 와 1 V 일 때, 각각 1와 2 V의 메모리 창 (memory window) 을 나타내었다. 드레인 전류-드레인 전압곡선에서 두 부분의 문턱전압에 의해 나타난 포화 드레인 전류차이는 게이트 전압이 0, 0.1, 0.2, 0.3 V 일 때, 각각 1.5, 2.7, 4.0, 5.7 mA로 명확한 차이를 나타내었다. PLZT(10/30/70), PLT(10), PZT(30/70) 박막의 이력곡선 시뮬레이션과 리텐션 특성의 fitting 결과를 바탕으로 시간경과 후의 드레인 전류를 분석한 결과, PLZT(10/30/70) 박막이 10년 후에도 약 18%의 포화 전류가 감소하는 가장 우수한 신뢰성을 나타내었다.

• Journal of Semiconductor Engineering
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• 제1권1호
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• pp.38-45
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• 2020

With the recent emergence of foldable electronic devices, interest in flexible organic memory is significantly growing. There are three types of flexible organic memory that have been researched so far: floating-gate (FG) memory, ferroelectric field-effect-transistor (FeFET) memory, and resistive memory. Herein, performance parameters and operation mechanisms of each type of memory device are introduced, along with a brief summarization of recent research progress in flexible organic memory.

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.25-28
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• 1999

Metal ferroelectric semiconductor Field Effect- Transistors(MFSFET) with various gate electrodes, that are aluminum, platinum and poly -Si, using LiNbO$_3$/Si(100) structures were fabricated and the properties of the FETs have been discussed. The drain current of the state of FET with Pt electrode was more than 3 orders of magnitude larger than the state current at the same gate voltage of 1.5 V, 7.rich means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about 10$^3$s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• Progress in Superconductivity
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• 제3권1호
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• pp.74-77
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• 2001

We have fabricated a high-Tc superconductive transistor with polyvinylidene fluoride (PVDF) gate electrode on MgO bicrystal Josephson junction by spin-coating method. The PVDF ferroelectric film is found to be suitable fur a gate electrode of the superconductive transistor since it has not only small leakage current but also high dieletric constant at low temperature. For the application of superconducting-FET, we investigated millimeter wave properties (60 GHz band) of the Josephson junction with PVDF gate electrode.