• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.9
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• pp.4645-4664
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• 2019

It is significant to construct deterministic measurement matrices with easy hardware implementation, good sensing performance and good cryptographic property for practical compressed sensing (CS) applications. In this paper, a deterministic construction method of bipolar chaotic measurement matrices is presented based on binary sequence family (BSF) and Chebyshev chaotic sequence. The column vectors of these matrices are the sequences of BSF, where 1 is substituted with -1 and 0 is with 1. The proposed matrices, which exploit the pseudo-randomness of Chebyshev sequence, are sensitive to the initial state. The performance of proposed matrices is analyzed from the perspective of coherence. Theoretical analysis and simulation experiments show that the proposed matrices have limited influence on the recovery accuracy in different initial states and they outperform their Gaussian and Bernoulli counterparts in recovery accuracy. The proposed matrices can make the hardware implement easy by means of linear feedback shift register (LFSR) structures and numeric converter, which is conducive to practical CS.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.1474-1477
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• 2009

본 논문에서는 ASR(Arithmetic Shift Register)과 SHA-2로 구성된 32비트 출력의 새로운 스트림 암호 ASC를 제안한다. ASC는 소프트웨어 및 하드웨어 구현이 쉽게 디자인된 스트림 암호 알고리즘이다. 특히 계산능력이 제한된 무선 통신장비에서 빠르게 수행할 수 있도록 개발되었다. ASC는 다양한 길이(8-32바이트)의 키를 지원하고 있으며, 워드 단위로 연산을 수행한다. ASC는 매우 간결한 구조를 가지고 있으며 선형 궤환 순서기(Linear Feedback Sequencer)로 ASR을 적용하였고, 비선형 순서기(Nonlinear sequencer)로 SHA-2를 적용하여 크게 두 부분으로 구성되어 있는 결합 함수(combining function) 스트림 암호이다. 그리고 8비트, 16비트, 32비트 프로세스에서 쉽게 구현이 가능하다. 제안한 스트림 암호 ASC는 최근에 표준 블록 암호로 제정된 AES, ARIA, SEED등의 블록 암호보다는 6-13배 빠른 결과를 보여주고 있으며, 안전성 또한 현대 암호 알고리즘이 필요로 하는 안전성을 만족하고 있다.

• International journal of advanced smart convergence
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• v.13 no.2
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• pp.35-43
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• 2024

In this paper, we propose two 127-bit LFSR (Linear Feedback Shift Register)-based OTP (One-Time Password) generators. One is a 9-digit decimal OTP generator with thirty taps, while the other is a 12-digit OTP generator with forty taps. The 9-digit OTP generator includes only the positions of Fibonacci numbers to enhance randomness, whereas the 12-digit OTP generator includes the positions of prime numbers and odd numbers. Both proposed OTP generators are implemented on an Arduino module, and randomness evaluations indicate that the generators perform well across six criteria and are straightforward to implement with Arduino.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2421-2429
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• 2000

With the advance of wireless communications technology, mobile communications have become more convenient than ever. Nowadays, people can communicate with each other on any place at any time. However, because of the openness of wireless communications, the way to protect the privacy between communicating parties is becoming a very important issue. In this paper, we present a study on the authentication and message encryption algorithm to support roaming service to the GSM network. To propose an authentication and message encryption algorithm applicable to the GSM system, the security architecture of the GSM outlined in the GSM standard is briefly introduced. In the proposed cryptosystems we use a new hash function for user authentication and a stream cipher based on Linear Feedback Shift Register(LFSR) for message encryption and decryption. Moreover, each algorithm is programmed with C language and simulated on IBM-PC system and we analyze the randomness properties of the proposed algorithms by using statistical tests.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.5
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• pp.137-145
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• 2003

Nowadays, people can communicate with each other on any time at my place by development of wireless communications. But, the openness of mobile communications Poses serious security threats and the security is necessary on mobile communications to support the secure communication channel. The most commonly method is stream cipher for mobile communications. Generally, this stream cipher is implemented by LFSR(Linear Feedback Shift Register). On this paper proposes the modified mechanism of the S box is usually used in block cipher to advance security og the stream cipher and this mechanism is the modified three one in consideration og the randomness. Generally, S box that is function with nonlinear property makes data more strong by attack. The randomness test of the proposed algorithm is used Ent Pseudorandom Number Sequence Test Program and by the test result it proves that it has better randomness and serial correlation value than the based stream cipher on respective test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.706-715
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• 2004

In this paper, to decide the watermark embedding positions and embed the watermark we use the subband tee structure which is presented in the wavelet domain and the edge information in the spatial domain. The significant frequency region is estimated by the subband searching from the higher frequency subband to the lower frequency subband. LH1 subband which has the higher frequency in tree structure of the wavelet domain is divided into 4${\times}$4 submatrices, and the threshold which is used in the watermark embedding is obtained by the blockmatrix which is consists by the average of 4${\times}$4 submatrices. Also the watermark embedding position, Keymap is generated by the blockmatrix for the energy distribution in the frequency domain and the edge information in the spatial domain. The watermark is embedded into the wavelet coefficients using the Keymap and the random sequence generated by LFSR(Linear feedback shift register). Finally after the inverse wavelet transform the watermark embedded image is obtained. the proposed watermarking algorithm showed PSNR over 2㏈ and had the higher results from 2％ to 8％ in the comparison with the previous research for the attack such as the JPEG compression and the general image processing just like blurring, sharpening and gaussian noise.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.9-15
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• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1235-1242
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• 2008

In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.