• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1247-1254
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• 2020

With the advent of the smart home era, equipment that provides confidentiality or performs authentication exists in various places in real life. Accordingly security against physical attacks is required for encryption equipment and authentication equipment. In particular, fault injection attack that artificially inject a fault from the outside to recover a secret key or bypass an authentication process is one of the very threatening attack methods. Fault sources used in fault injection attacks include lasers, electromagnetic, voltage glitches, and clock glitches. Fault injection attacks are classified into single fault injection attacks and multiple fault injection attacks according to the number of faults injected. Existing multiple fault injection systems generally use a single fault source. The system configured to inject a single source of fault multiple times has disadvantages that there is a physical delay time and additional equipment is required. In this paper, we propose a multiple fault injection system using heterogeneous fault sources. In addition, to show the effectiveness of the proposed system, the results of a multiple fault injection attack against Riscure's Piñata board are shown.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.10
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• pp.5123-5129
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• 2013

In this paper, it is proposed that JTAG fault injection environment and the results of the classification techniques that the reliability of embedded systems can be tested. As applying these, this is possible to quantitative analysis of vulnerable factor for system. The quantitative analysis for the degree of vulnerability of system is evaluated by faults errors, and failures classification schemes. When applying these schemes, it is possible to verify process and classify for fault that might occur in the system.

• ETRI Journal
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• v.33 no.1
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• pp.50-59
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• 2011

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

• Nuclear Engineering and Technology
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• v.51 no.3
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• pp.692-701
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• 2019

Recently, instrumentation and control (I&C) systems in nuclear power plants have undergone digitalization. Owing to the unique characteristics of digital I&C systems, the reliability analysis of digital systems has become an important element of probabilistic safety assessment (PSA). In a reliability analysis of digital systems, fault-tolerant techniques and their effectiveness must be considered. A fault injection experiment was performed on a safety-critical digital I&C system developed for nuclear power plants to evaluate the effectiveness of fault-tolerant techniques implemented in the target system. A software-implemented fault injection in which faults were injected into the memory area was used based on the assumption that all faults in the target system will be reflected in the faults in the memory. To reduce the number of required fault injection experiments, the memory assigned to the target software was analyzed. In addition, to observe the effect of the fault detection coverage of fault-tolerant techniques, a PSA model was developed. The analysis of the experimental result also can be used to identify weak points of fault-tolerant techniques for capability improvement of fault-tolerant techniques

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.4
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• pp.305-311
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• 2005

Flash memory software running on cellular phones and PDAs need to be tested extensively to cope with abrupt power and media faults. For those tests, we designed and implemented a Flash memory emulator with fault injection features. The fault injection tester has provided a helpful framework for designing fault recovery schemes and also for analyzing fault damages to the FTL (Flash Translation Layer) and file system for a Flash memory based system. In this paper, we discuss Plash memory fault types and fault injection features implemented on this Flash memory emulator. We then discuss in detail a design flaw revealed during fault injection tests. Specifically, it was revealed that a scheme that was believed to improve reliability instead, turned out to be harmful. In addition, we discuss post-fault behaviors of the FTL and the file system.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.5
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• pp.195-200
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• 2009

CRT-based RSA algorithm, which was implemented on smartcard, microcontroller and so on, leakages secret primes p and q by fault attacks using laser injection, EM radiation, ion beam injection, voltage glitch injection and so on. Among the many fault injection methods, voltage glitch can be injected to target device without any modification, so more practical. In this paper, we made an experiment on the fault injection attack using abnormal source voltage. As a result, CRT-RSA's secret prime p and q are disclosed by fault attack with voltage glitch injection which was introduced by several previous papers, and also succeed the fault attack with source voltage blocking for proper period.

• Journal of Power Electronics
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• v.19 no.4
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• pp.968-979
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• 2019

Recently, there has been increased interest in the study of multiphase machines due to their higher fault-tolerant capability when compared to their conventional three-phase counterparts. For six-phase machines, stator windings configured with a single isolated neutral (1N) provide significantly more post-fault torque/power than two isolated neutrals (2N). Hence, this configuration is preferred in applications where post-fault performance is critical. It is well known that min-max injection has been commonly used for three-phase and multiphase machines in healthy condition to maximize the modulation limit. However, there is a lack of discussion on min-max injection for post-fault condition. Furthermore, the effects in terms of the common-mode voltage (CMV) in modulating signals has not been discussed. This paper investigates the effect of min-max injection in post fault-tolerant control on the voltage and speed limit of a symmetrical six-phase induction machine with single isolated neutral. It is shown that the min-max injection can minimize the amplitude of reference voltage, which maximizes the modulation index and post-fault speed of the machine. This in turn results in a higher post-fault power.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.5
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• pp.965-973
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• 2022

As IoT(Internet of Things) devices become common, many algorithms have been developed to protect users' personal information. The laser fault injection attack that threatens those algorithms is a side-channel analysis that intentionally injects a laser beam to the outside of a device to acquire confidential information or abnormal privileges of the system. There are many studies to determine the timing of fault injection to reduce the number of necessary fault injections, but the location to inject faults is only repeatedly searched for the entire area of the device. However, when fault injection is performed in an algorithm-independent area, the attacker cannot obtain the intended faulted statement or attempt to bypass authentication, so finding areas vulnerable to fault injection and performing an attack is an important consideration in achieving a high attack success rate. In this paper, we show that a 100% attack success rate can be achieved by determining the vulnerable areas for fault injection by using electromagnetic and thermal information generated from the device's chip. Based on this, we propose an efficient fault injection attack system.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.11
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• pp.958-962
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• 2003

We acquired data of injection molding machine in operation and stored the data in database. We acquired the data of injection molding machine for fault detection and diagnosis (FDD) continuously and estimated the fault results with a fuzzy algorithm. Many of FDD are applied to a huge system, nuclear power plant and a computer numerical control(CNC) machine for processing machinery. But, the research of FDD is rare in injection molding machine compare with computer numerical control machine. We appraise the accuracy of the FDD and the limit of the application to the injection molding machine. We construct the fault detection and diagnosis system based on fuzzy algorithm in the injection molding machine. Data of operating injection molding machine are acquired in order to improve the reliability of detection and diagnosis.

• Nuclear Engineering and Technology
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• v.54 no.6
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• pp.2031-2036
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• 2022

Energetic particle strikes the device and induces data corruption in the configuration memory (CRAM), causing errors and even malfunctions in a system on chip (SoC). Software-based fault injection is a convenient way to assess device performance. In this paper, dynamic partial reconfiguration (DPR) is adopted to make fault injection on a Xilinx 16 nm FinFET Ultrascale+ MPSoC. And the reconfiguration module implements the Sobel and Gaussian image filtering, respectively. Fault injections are executed on the static and reconfiguration modules' bitstreams, respectively. Another contribution is that the failure modes and effects analysis (FMEA) method is applied to evaluate the system reliability, according to the obtained injection results. This paper proposes a software-based solution to estimate programmable device vulnerability.