• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.319-329
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• 2016

High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

• Journal of Semiconductor Engineering
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• 제2권1호
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• 대한전자공학회논문지SD
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• 제46권3호
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• pp.51-59
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• 2009

본 논문에서는 어쿠스틱 센서 IC 용 연속 시간 시그마-델타 모듈레이터를 구현하였다. 모듈레이터의 전력 소모를 최소화하기 위해 summing 단의 필요성을 제거한 피드-포워드 (feed-forward) 구조로 설계 하였으며, 해상도를 높이기 위해 선형성이 우수한 active-RC 필터를 사용하여 설계 하였다. 또한 초과 루프 지연 시간 (excess loop delay)에 의한 성능 저하를 방지하기 위한 회로 기법을 제안 하였다. 저 전압, 고 해상도의 4차 단일 비트 연속 시간 시그마-델타 모듈레이터는 $0.13{\mu}m$ 1 poly 8 metal CMOS 표준 공정으로 제작하였으며 코어 크기는 $0.58\;mm^2$ 이다 시뮬레이션 결과 25 kHz 의 신호 대역 내에서 91.3 dB의 SNR(signal to noise ratio)을 얻었고 전체 전력 소모는 $290{\mu}W$ 임을 확인하였다.

• 대한전자공학회논문지SD
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• 제44권8호
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• pp.65-73
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• 2007

본 논문에서는 UMTS용 수신기를 위한 저 전력 CMOS 연속-시간 시그마-델타 모듈레이터에 대해 논한다. 저 전력 동작수행을 위한 연속 시간 모듈레이터의 루프 필터는 선형성이 우수하고, 튜닝 회로가 비교적 간단한 active-RC 필터로 구성하였다. 본 모듈레이터의 구조는 전력 효율을 높이기 위해 24의 OSR (Oversampling Ratio)의 3차 4비트 단일 루프로 구성하였고, 초과 루프 지연 시간에 의한 성능 저하를 방지하기 위해 반주기 지연 제환 경로를 추가하였다. 제작한 회로의 SNR, SNDR, Dynamic range는 각각 71dB, 65dB, 74dB로 측정되었다. 설계한 연속-시간 시그마-델타 모듈레이터는 0.18-um CMOS 표준공정으로 제작하였고, 1.8V의 단일 전원 전압에서 15mW의 전력을 소모한다.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1995년도 추계학술발표회논문집(2)
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• pp.562-567
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• 1995

The concept of VLDT (Variable Low DNBR Trip), a new CPC trip function, was proposed and applied to the events of increase in secondary heat removal, such as an excess feedwater event anti an IOSGADV (Inadvertent Opening S/G Atmospheric Dump Valve). Major assumption used in this study was no time delay to LOOP (Loss of Offsite Power) after turbine trip. In case of using this VLDT function, safety criterion of DNB would not be violated under the same condition as previous analysis without any change in thermal margin.

• International Journal of Automotive Technology
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• 제8권4호
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• pp.437-444
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• 2007

This paper experimentally investigates the effects of oxygen-enriched air (OEA) on the running behaviors of an LPG SI engine during both start/warm-up (SW) and hot idling (HI) stages. The experiments were performed on an air-cooled, single-cylinder, 4-stroke, LPG SI engine with an electronic fuel injection system and an electrically-heated oxygen sensor. OEA containing 23% and 25% oxygen (by volume) was supplied for the experiments. The throttle position was fixed at that of idle condition. A fueling strategy was used as following: the fuel injection pulse width (FIPW) in the first cycle of injection was set 5.05 ms, and 2.6 ms in the subsequent cycles till the achieving of closed-loop control. In closed-loop mode, the FIPW was adjusted by the ECU in terms of the oxygen sensor feedback. Instantaneous engine speed, cylinder pressure, engine-out time-resolved HC, CO and NOx emissions and excess air coefficient (EAC) were measured and compared to the intake air baseline (ambient air, 21% oxygen). The results show that during SW stage, with the increase in the oxygen concentration in the intake air, the EAC of the mixture is much closer to the stoichiometric one and more oxygen is made available for oxidation, which results in evidently-improved combustion. The ignition in the first firing cycle starts earlier and peak pressure and maximum heat release rate both notably increase. The maximum engine speed is elevated and HC and CO emissions are reduced considerably. The percent reductions in HC emissions are about 48% and 68% in CO emissions about 52% and 78%; with 23% and 25% OEA, respectively, compared to ambient air. During HI stage, with OEA, the fuel amount per cycle increases due to closed-loop control, the engine speed rises, and speed stability is improved. The HC emissions notably decrease: about 60% and 80% with 23% and 25% OEA, respectively, compared to ambient air. The CO emissions remain at the same low level as with ambient air. During both SW and HI stages, intake air oxygen enrichment causes the delay of spark timing and the increased NOx emissions.