• 전기전자학회논문지
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• 제13권4호
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• pp.23-27
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• 2009

실리콘 기판 상에 MBE (molecular beam epitaxy)로 형성된 GaSb 기반 p-channel HEMT 소자를 제작하기 위하여 오믹 접촉 형성 공정과 식각 공정을 연구하였다. 먼저 각 소자의 절연을 위한 메사 식각 공정 연구를 수행하였으며, HF기반의 습식 식각 공정과 ICP(inductively coupled plasma)를 이용한 건식 식각 공정이 모두 사용되었다. 이와 함께 소스/드레인 영역 형성을 위한 오믹 접촉 형성 공정에 관한 연구를 진행하였으며 Ge/Au/Ni/Au 금속층 및 $300^{\circ}C$ 60초 RTA공정을 통해 $0.683\;{\Omega}mm$의 접촉 저항을 얻을 수 있었다. 더불어 HEMT 소자의 게이트 형성을 위한 게이트 리세스 공정을 AZ300 현상액과 citric산 기반의 습식 식각을 이용하여 연구하였으며, citric산의 경우 소자 구조에서 캡으로 사용된 GaSb와 베리어로 사용된 AlGaSb사이에서 높은 식각 선택비를 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.942-945
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• 1999

In this work, we proposed Proper etching algorithm for ultra-large scale integrated circuit device and simulated etching process using the proposed algorithm in the case of ICP (inductive coupled plasma) 〔1〕source. Until now, many algorithms for etching process simulation have been proposed such as Cell remove algorithm, String algorithm and Ray algorithm. These algorithms have several drawbacks due to analytic function; these algorithms are not appropriate for sub 0.1 ${\mu}{\textrm}{m}$ device technologies which should deal with each ion. These algorithms could not present exactly straggle and interaction between Projectile ions and could not consider reflection effects due to interactions among next projectile ions, reflected ions and sputtering ions, simultaneously In order to apply ULSI process simulation, algorithm considering above mentioned interactions at the same time is needed. Proposed algorithm calculates interactions both in plasma source region and in target material region, and uses BCA (binary collision approximation4〕method when ion impact on target material surface. Proposed algorithm considers the interaction between source ions in sheath region (from Quartz region to substrate region). After the collision between target and ion, reflected ion collides next projectile ion or sputtered atoms. In ICP etching, because the main mechanism is sputtering, both SiO$_2$ and Si can be etched. Therefore, to obtain etching profiles, mask thickness and mask composition must be considered. Since we consider both SiO$_2$ etching and Si etching, it is possible to predict the thickness of SiO$_2$ for etching of ULSI.

• 한국정밀공학회지
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• 제19권5호
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• pp.149-158
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• 2002

Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.

• 한국재료학회지
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• 제27권4호
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• pp.211-215
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• 2017

Reactive Ion Etching (RIE) and wet etching are employed in existing texturing processes to fabricate solar cells. Laser etching is used for particular purposes such as selective etching for grooves. However, such processes require a higher level of cost and longer processing time and those factors affect the unit cost of each process of fabricating solar cells. As a way to reduce the unit cost of this process of making solar cells, an atmospheric plasma source will be employed in this study for the texturing of crystalline silicon wafers. In this study, we produced the atmospheric plasma source and examined its basic properties. Then, using the prepared atmospheric plasma source, we performed the texturing process of crystalline silicon wafers. The results obtained from texturing processes employing the atmospheric plasma source and employing RIE were examined and compared with each other. The average reflectance of the specimens obtained from the atmospheric plasma texturing process was 7.88 %, while that of specimens obtained from the texturing process employing RIE was 8.04 %. Surface morphologies of textured wafers were examined and measured through Scanning Electron Microscopy (SEM) and similar shapes of reactive ion etched wafers were found. The Power Conversion Efficiencies (PCE) of the solar cells manufactured through each process were 16.97 % (atmospheric plasma texturing) and 16.29 % (RIE texturing).

• Transactions on Electrical and Electronic Materials
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• 제11권4호
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• pp.174-177
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• 2010

We have developed an environment-friendly etching process, an alternative to the dichromic acid etching process, as a pretreatment of acrylonitrile-butadiene-styrene (ABS) plastic for electroless plating. In order to plate ABS plastic in an electroless way, there should be fine holes on the surface of the ABS plastic to enhance mechanically the adhesion strength between the plastic surface and the plate. To make these holes, the surface was coated uniformly with dispersed chemical foaming agents in a mixture of environmentally friendly dispersant and solvent by the methods of dipping or direct application. The solvent seeps into just below the surface and distributes the chemical foaming agents uniformly beneath the surface. After drying off the surface, the surface was heated at a temperature well below the glass transition temperature of ABS plastic. By pyrolysis, the chemical foaming agents made fine holes on the surface. In order to discover optimum conditions for the formation of fine holes, the mixing ratio of the solvent, the dispersant and the chemical foaming agent were controlled. After the etching process, the surface was plated with nickel. We tested the adhesion strength between the ABS plastic and nickel plate by the cross-cutting method. The surface morphologies of the ABS plastic before and after the etching process were observed by means of a scanning electron microscope.

• Current Photovoltaic Research
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• 제1권1호
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• pp.69-72
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• 2013

Combined nano- and micro-wires (CNMWs) Si arrays were prepared using PR patterning and silver-assisted electroless etching. A $POCl_3$ doping process was applied to the fabrication of CNMWs solar cells. KOH solution was used to remove bundles in CNMWs and the etching time was varied from 30 to 240 s. The lowest reflectance of 3.83% was obtained at KOH etching time of 30 s, but the highest carrier lifetime of $354{\mu}s$ was observed after the doping process at 60 s. At the same etching time, a $V_{oc}$ of 574 mV, $J_{sc}$ of $28.41mA/cm^2$, FF of 74.4%, and Eff. of 12.2% were achieved in the CNMWs solar cell. CNMWs solar cells have potential for higher efficiency by improving the post-process and surface-rear side structure.

• 제어로봇시스템학회논문지
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• 제4권2호
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• pp.246-255
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• 1998

This paper presents a novel method for real-time malfunction detection of plasma etching process using EPD signal traces. First, many reference EPD signal traces are collected using monochromator and data acquisition system in normal etching processes. Critical points are defined by applying differentiation and zero-crossing method to the collected reference signal traces. Critical parameters such as intensity, slope, time, peak, overshoot, etc., determined by critical points, and frame attributes transformed signal-to symbol of reference signal traces are saved. Also, UCL(Upper Control Limit) and LCL(Lower Control Limit) are obtained by mean and standard deviation of critical parameters. Then, test EPD signal traces are collected in the actual processes, and frame attributes and critical parameters are obtained using the above mentioned method. Process malfunctions are detected in real-time by applying SPC(Statistical Process Control) method to critical parameters. the Real-time malfunction detection method presented in this paper was applied to actual processes and the results indicated that it was proved to be able to supplement disadvantages of existing quality control check inspecting or testing random-selected devices and detect process malfunctions correctly in real-time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.859-862
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• 2001

This study describes a selective Ag etching solution for use with pattern on the surface of copper. This etching solution uses potassium iodide and potassium sulfate as the ligand that coordinates to the metal ions and ferricyanide as the oxidant. The etching rate was depended on the concentration of co-ligands and time. But the etching rate wasn't depended on the pH(2∼6), and oxidant(K$_3$Fe(CN)$\_$6/). Complete etching of silver can be achieved rapidly within 90sec for 4.46${\mu}$m thick metal films when aqueous solutions containing K$_3$Fe(CN)$\_$6/, K$_2$S$_2$O$\_$8/ and KI was used. This etching solution was characteristic of anisotropic etching.

• 전기학회논문지
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• 제56권12호
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• pp.2221-2225
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• 2007

Hollow-type microneedle array can be used for painless, continuous and stable drug delivery through a human skin. The needles must be sharp and have sufficient length in order to penetrate the epidermis. An array of hollow-type silicon microneedles was fabricated by using deep reactive ion etching and HNA wet etching with two oxide masks. Isotropic etching was used to create tapered tips of the needles, and anisotropic etching of Bosch process was used to make the extended length and holes of microneedles. The microneedles were formed by three steps of isotropic, anisotropic, and isotropic etching in order. The holes were made by one anisotropic etching step. The fabricated microneedles have $170{\mu}m$ width, $40{\mu}m$ hole diameter and $230{\mu}m$ length.

• 센서학회지
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• 제30권1호
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• pp.10-14
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• 2021

Wet etching is more economical than dry etching and provides a uniform etching depth regardless of wafer sizes. Typically, potassium hydroxide (KOH) and tetra-methyl-ammonium hydroxide (TMAH) solutions are widely used for the wet etching of silicon. However, there is a limit to the wet etching process when a material deposited on an unetched surface reacts with an etching solution. To solve this problem, in this study, an apparatus was designed and manufactured to physically block the inflow of etchants on the surface using a rubber O-ring. The proposed apparatus includes a heater and a temperature controller to maintain a constant temperature during etching, and the hydrostatic pressure of the etchant is considered for the thin film structure. A corrugation membrane with a diameter of 800 ㎛, thickness of 600 nm, and corrugation depth of 3 ㎛ with two corrugations was successfully fabricated using the prepared device.