• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.19-23
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• 2012

Silicon substrate for light emitting diodes (LEDs) has been the tendency of LED packaging for improving power consumption and light output. In this study, a low cost and high throughput Si through via fabrication has been demonstrated using a wet etching process. Both a wet etching only process and a combination of wet etching and dry etching process were evaluated. The silicon substrate with Si through via fabricated by KOH wet etching showed a good electrical resistance (${\sim}5.5{\Omega}$) of Cu interconnection and a suitable thermal resistance (4 K/W) compared to AlN ceramic substrate.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.169-172
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• 2015

Although, there are several research studies on the engineering of the graphene layers using different etching techniques, there is not any comprehensive study on the effects of using different etching masks in the reactive ion etching (RIE) method on the quality and uniformity of the etched graphene films. This study investigated the effects of using polystyrene and conventional photolithography resist as a etching mask on the engineering of the number of graphene layers, using RIE. The effects were studied using Raman spectroscopy. This analysis indicated that the photo-resist mask is better than the polystyrene mask because of its lower post processing effects on the graphene surface during the RIE process. A single layer graphene was achieved from a bi-layer graphene after 3 s of the RIE process using oxygen plasma, and the bi-layer graphene was successfully etched after 6 s of the RIE process. The bilayer etching time was significantly smaller than reported values for graphene flakes in previous research.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.7 s.172
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• pp.71-78
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• 2005

The purpose of this study is to suggest a hyperfine maskless writing technique by using the nanoindentation and HF wet etching technique. Indents were made on the surface of Pyrex7740 glass by the hyperfine indentation process with a Berkovich diamond indenter, and they were etched in $50\;wr\%$ HF solution. After etching process, convex structure was obtained due to the deformation-induced hillock phenomena. In this study, effects of indentation process parameters (etching time, normal load, loading .ate, hold-time at the maximum load) on the morphologies of the indented surfaces after isotopic etching were investigated from an angle of deformation energies. Finally, sample characters were written to show the possibility of the application.

• Journal of information and communication convergence engineering
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• v.5 no.3
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• pp.215-218
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• 2007

In this paper, amorphous semiconductor and insulator thin film are etched using reactive ion etcher. At that time, we experiment in various RIE conditions (chamber pressure, gas flow rate, rf power, temperature) that have effects on quality of thin film. The using gases are $CF_4,\;CF_4+O_2,\;CCl_2F_2,\;CHF_3$ gases. The etching of a-Si:H thin film use $CF_4,\;CF_4+O_2$ gases and the etching of $a-SiO_2,\;a-SiN_x$ thin film use $CCl_2F_2,\;CHF_3$ gases. The $CCl_2F_2$ gas is particularly excellent because the selectivity of between a-Si:H thin film and $a-SiN_x$ thin film is 6:1. We made precise condition on dry etching with uniformity of 5%. If this dry etching condition is used, that process can acquire high yield and can cut down process cost.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.05a
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• pp.225-228
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• 2005

The purpose of this study is to investigate effects of the plastic/elastic deformation energy on wet etching characterization on the surface of material by using the nanoindentation and HF wet etching technique. Indents were made on the surface of Pyrex 7740 glass by the hyperfine indentation process with a Berkovich diamond indenter, and they were etched in $50\;wt\%$ HF solution. After etching process, convex structure was obtained due to the deformation-induced hillock phenomena. In this study, effects of indentation process parameters (normal load, loading rate) on the morphologies of the indented surfaces after isotopic etching were investigated from an angle of deformation energies.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.28 no.1
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• pp.109-117
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• 2004

The objective of this study is to investigate the effect of the spray characteristics on the etching characteristics for the optimization of etching process in the micro fabrication industry. The etching characteristics such as etching rate and etching factor were investigated under different etching conditions. To compare with the etching characteristic, the spray characteristics such as droplet size and velocity were measured by PDA system. The etching rate was increased in case of high spray pressure and in the region of spray center. The etching factor was increased with decrease in the distance from nozzle tip and increase in the etchant temperature. It was found that the spray characteristics were correlated with the etching characteristics.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.3
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• pp.143-147
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• 2017

To evaluate surface characteristics and improve crystalline quality of AlN single crystal grown by physical vapor transport (PVT) method, wet chemical etching process using $KOH/H_2O_2$ mixture in a low temperature condition and thermal annealing process was proceeded respectively. Conventional etching process using strong base etchant at a high temperature (above $300^{\circ}C$) had formed over etching phenomenon according to crystalline quality of materials. When it occurred to over etching phenomenon, it had a low reliability of dislocation density because it cannot show correct number of etch pits per estimated area. Therefore, it was proceeded to etching process in a low temperature (below $100^{\circ}C$) using $H_2O_2$ as an oxidizer in KOH aqueous solution and to be determined optimum etching condition and dislocation density via scanning electron microscope (SEM). For improving crystalline quality of AlN single crystal, thermal annealing process was proceeded. When compared with specimens as-prepared and as-annealed, full width at half maximum (FWHM) of the specimen as-annealed was decreased exponentially, and we analyzed the mechanism of this process via double crystal X-ray diffraction (DC-XRD).

• ETRI Journal
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• v.27 no.3
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• pp.304-311
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• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1485-1488
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• 1997

The capacity of memory chip has increased vert quickly and 64MDRAM becomes main product in semiconductor manufacturing lines consists of many sequential processes, including etching process. although it needs direct sensing of wafer state for the accurae detching, it depends on indirect esnsing and sample test because of the complexity of the plasma etching. This equipment receives the inner light of etch chamber through the viewport and convets it to the voltage inetnsity. In this paper, EDP voltage signal has a new role to detect etching failure. First, we gathered data(EPD sigal, etching time and etchrate) and then analyzed the relationships between the signal variatin and the etch rate using two neural network modeling. These methods enable to predict whether ething state is good or not per wafer. For experiments, it is used High Density Inductive coupled Plasma(HDICP) ethcing equipment. Experiments and results proved to be abled to determine the etching state of wafer on-line and analyze the causes by modeling and EPD signal data.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1045-1048
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• 2003

In this paper, we studied plasma damage of MIS capacitor with $Al_2$O$_3$ dielectric film. Using capacitor pattern with the same area but different perimeters, we tried to separate etching damage mechanism and to optimize the dry etching process. After etching both metal and dielectric layer by the same condition, leakage current and C-V measurements were carried out for Pt/A1$_2$O$_3$/Si structures. The flatband voltage shift was appeared in the C-V plot, and it was caused by the variation of the fixed interface charge and the interface trapped charge. From I-V measurement, it was found the leakage current along the periphery could not be ignored. Finally, we established the process condition of RF power 300W, 100mTorr, Ar/Cl$_2$ gas 60sccm as an optimal etching condition.