• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.50 no.9
• /
• pp.438-443
• /
• 2001

In the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control, within-wafer-non-uniformity, and the possible defects such as pad oxide damage and nitride residue. The defect like nitride residue and silicon (or pad oxide) damage after STI-CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI fill and STI-CMP were discussed. Consequently, we could conclude that law trench depth and high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.501-504
• /
• 1999

In the shallow trench isolation(STI) chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control within- wafer-non-uniformity, and the possible defects such as nitride residue and pad oxide damage. These defects after STI CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI filling and STI CMP were discussed. It is represented that the nitride residue can be occurred in the condition of high post CMP thickness and low trench depth. In addition there are remaining oxide on the moat surface after reverse moat etch. It means that reverse moat etching process can be the main source of nitride residue. Pad oxide damage can be caused by over-polishing and high trench depth.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.7
• /
• pp.60-74
• /
• 1993

Experiments of RIE of tungsten films using SF$_{6}$ plasma were conducted to investigate the effect of process parameters on etch rate, uniformity, anisotropy, and selectivity. As power increased, the etch rate increased. Maximum etch rate was obtained at 200mtorr As interelectrode spacing increased the etch rate increased for P < 200mtorr while it decreased for P> 200mtorr. Etch rate was maximum at 20 sccm gas flow rate. As substrate temperature increased, the etch rate increased and activation energy was 0.046 eV. In addition, maximum etch rate was acquired at 20% $O_{2}$ addition. The etch rate slightly increased when Ar was added up to 20% while it continuously decreased when N$_{2}$ was added. Uniformity got improved as pressure decreased and was less than 4% for P <100mtorr. Mass spectrometer was utilized to analyze gas composition and S and F peaks were observed from XPS analysis with increasing power. The anisotropy was better for smaller power and spacing, and lower pressure and temperature. It improved when CH$_{4}$ was added and anisotropic etch profile was obtained when about 10% $O_{2}$ was added. The selectjvity was better for smaller power larger pressure and spacing, and lower temperature. Especially. low temperature processing was proposed as a novel method to improve the anisotropy and selectivity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.04b
• /
• pp.147-151
• /
• 2000

This paper presents the electrochemical etch-stop characteristics of single-crystal silicon in a tetramethyl ammonium hyciroxide(TMAH):isopropyl alcohol(IPA):pyrazine solution. Addition of pyrazine to a TMAH:IPA etchant increases the etch-rate of (100) silicon, thus the elapsed time for etch-stop was shortened. The current-voltage(I-V) characteristics of n- and p-type silicon in a TMAH:IPA:pyrazine solution were obtained, respectively. Open circuit potential(OCP) and passivation potential(PP) of n- and p-type silicon, respectively, were obtained and applied potential was selected between n- and p-type silicon PP. The electrochemical etch-stop is applied to the fabrication of 801 microdiaphragms having $20\;{\mu}m$ thickness on a 5-inch silicon wafer. The averge thicknesses of 801 microdiaphragms fabricated on the one wafer were $20.03\;{\mu}m$ and standard deviation was ${\pm}0.26{\mu}m$. The silicon surface of the etch-stopped microdiaphragm was extremely flat without noticeable taper or other nonuniformities. The benefits of the electrochemical etch-stop in a TMAH:IPA:pyrazine solution become apparent when reproducibility in the microdiaphragm thickness for mass production is considered. These results indicate that the electrochemical etch-stop in a TMAH:IPA:pyrazine solution provides a powerful and versatile alternative process for fabricating high-yield silicon microdiaphragms.

• Journal of the Optical Society of Korea
• /
• v.6 no.4
• /
• pp.180-184
• /
• 2002

In this study, we investigated mask errors, photo errors with attenuated phase shift mask and off-axis illumination, and etch errors in dry etch conditions. We propose that total process proximity correction (TPPC), a concept merging every process step error correction, is essential in a lithography process when minimum critical dimension (CD) is smaller than the wavelength of radiation. A correction rule table was experimentally obtained applying TPPC concept. Process capability of controlling gate CD in DRAM fabrication should be improved by this method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.363-363
• /
• 2008

The development of dry etching process for sapphire wafer with plasma has been key issues for the opto-electric devices. The challenges are increasing control and obtaining low plasma induced-damage because an unwanted scattering of radiation is caused by the spatial disorder of pattern and variation of surface roughness. The plasma-induced damages during plasma etching process can be classified as impurity contamination of residual etch products or bonding disruption in lattice due to charged particle bombardment. Therefor, fine pattern technology with low damaged etching process and high etch rate are urgently needed. Until now, there are a lot of reports on the etching of sapphire wafer with using $Cl_2$/Ar, $BCl_3$/Ar, HBr/Ar and so on [1]. However, the etch behavior of sapphire wafer have investigated with variation of only one parameter while other parameters are fixed. In this study, we investigated the effect of pressure and other parameters on the etch rate and the selectivity. We selected $BCl_3$ as an etch ant because $BCl_3$ plasmas are widely used in etching process of oxide materials. In plasma, the $BCl_3$ molecule can be dissociated into B radical, $B^+$ ion, Cl radical and $Cl^+$ ion. However, the $BCl_3$ molecule can be dissociated into B radical or $B^+$ ion easier than Cl radical or $Cl^+$ ion. First, we evaluated the etch behaviors of sapphire wafer in $BCl_3$/additive gases (Ar, $N_2,Cl_2$) gases. The behavior of etch rate of sapphire substrate was monitored as a function of additive gas ratio to $BCl_3$ based plasma, total flow rate, r.f. power, d.c. bias under different pressures of 5 mTorr, 10 mTorr, 20 mTorr and 30 mTorr. The etch rates of sapphire wafer, $SiO_2$ and PR were measured with using alpha step surface profiler. In order to understand the changes of radicals, volume density of Cl, B radical and BCl molecule were investigated with optical emission spectroscopy (OES). The chemical states of $Al_2O_3$ thin films were studied with energy dispersive X-ray (EDX) and depth profile anlysis of auger electron spectroscopy (AES). The enhancement of sapphire substrate can be explained by the reactive ion etching mechanism with the competition of the formation of volatile $AlCl_3$, $Al_2Cl_6$ or $BOCl_3$ and the sputter effect by energetic ions.

• Journal of the Semiconductor & Display Technology
• /
• v.16 no.2
• /
• pp.55-60
• /
• 2017

The supercritical $CO_2$ (sc-$CO_2$) mixture and the sc-$CO_2$-based Photoresist(PR) stripping(SCPS) process were applied to the removal of the post etch/ash PR residue on aluminum patterned wafers and the results were observed by scanning of electron microscope(SEM). In the case of MDII wafers, the carbonized PR was able to be effectively removed without pre-stripping by oxygen plasma ashing by using sc-$CO_2$ mixture containing the optimum formulated additives at the proper pressure and temperature, and the same result was also able to be obtained in the case of HDII wafer. It was found that the efficiency of SCPS of ion implanted wafer improved as the temperature of SCPS was high, so a very large amount of MEA in the sc-$CO_2$ mixture could be reduced if the temperature could be increased at condition that a process permits, and the ion implanted photoresist(IIP) on the wafer was able to be removed completely without pre-treatment of plasma ashing by using the only 1 step SCPS process. By using SCPS process, PR polymers formed on sidewalls of metal conductive layers such as aluminum films, titanium and titanium nitride films by dry etching and ashing processes were removed effectively with the minimization of the corrosion of the metal conductive layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.741-744
• /
• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Journal of the Korean Vacuum Society
• /
• v.8 no.4A
• /
• pp.476-481
• /
• 1999

Characteristics of platinum dry etching were investigated in a cryogenic magnetized inductively coupled plasma (MICP). The problem with platinum etching is the redeposition of sputtered platinum on the sidewall. Because of the redeposits on the sidewall, the etching of patterned platinum structure produces feature sizes that exceed the original dimension of the PR size and the etch profile has needle-like shape [1]. The main object of this study was to investigate a new process technology for fence-free Pt etching As bias voltage increased, the height of fence was reduced. In cryogenic etching, the height of fence was reduced to 20% at-$190^{\circ}C$ compared with that of room temperature, however the etch profile was not still fence-free. In Ar/$SF_6$ Plasma, fence-free Pt etching was possible. As the ratio of $SF_6$ gas flow is more than 14% of total gas flow, the etch profile had no fence. Chemical reaction seemed to take place in the etch process.

• Proceedings of the KIEE Conference
• /
• 2001.07c
• /
• pp.1890-1892
• /
• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -750 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.