• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• 한국통신학회논문지
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• 제32권3C호
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• pp.195-204
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• 2007

The cyclic redundancy check(CRC) code used to decide retransmission request in hybrid automatic repeat request(HRAQ) system can also be used to stop iterative decoding of turbo code if it is used as an error correcting code(ECC) of HARQ system. Thus a scheme to use CRC code for both iteration stop and repeat request in the HARQ system with turbo code based on the standard of cdma 2000 system is proposed in this paper. At first, the optimum CRC code which has the minimum length without performance degradation due to undetected errors is found. And the most appropriate turbo encoder structure is also suggested. As results, it is shown that at least 32-bit CRC code should be used and a turbo code with 3 constituent encoders is considered to be the most appropriate one.

• 전기전자학회논문지
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• 제21권2호
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• pp.130-135
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• 2017

Normally, in data transmission, extra parity bits are added to the input message which were derived from its input and a pre-defined algorithm. The same algorithm is used by the receiver to check the consistency of the delivered information, to determine if it is corrupted or not. It recovers and compares the received information, to provide matching and correcting the corrupted transmitted bits if there is any. This paper aims the following objectives: to use an alternative error detection-correction method, to lessens both the fixed number of the required redundancy bits 'r' in cyclic redundancy checking (CRC) because of the required polynomial generator and the overhead of interspersing the r in Hamming code. The experimental results were synthesized using Xilinx Virtex-5 FPGA and showed a significant increase in both the transmission rate and detection of random errors. Moreover, this proposal can be a better option for detecting and correcting errors.

• 한국통신학회논문지
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• 제21권7호
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• pp.1787-1802
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• 1996

In this paper, the performance for FH/CPFSK system with limiter-discriminator detection and integrage-and-dump post-detection filtering under thermal noie, partial-band noise jamming and rayleigh fading have been analyzed. The method of hard-decision diversity of which the transmitter repeated L times on different hops for each data symbol in a way to mutigate the effects of the jamming has been applied, and the receiver has been combined the L chips. Also, error-correcting code have been applied for improving performance of system. The thermal noise and partial-band noise jamming, intersymbol interference for all eight of the possible adjacent bit data patterns, and FM noise click for evaluating systems have been considered. Also optimum parameters to improve performance of FH/CPFSK system have been obtained and validities have been proved through computer simulation.

• 대한수학회논문집
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• 제20권2호
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• pp.405-409
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• 2005

In [1], Sharma and Goel obtained a bound for random error correcting codes with Lee weight considerations. The purpose of this paper is to first point out a discrepancy in this result and then give a correct version of the same, improving upon the bound tremendously.

• Journal of Electrical Engineering and information Science
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• 제1권1호
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• pp.23-28
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• 1996

In this series of two papers, adaptive code rate change schemes in DS-SSMA systems are proposed. In the proposed schemes the error correcting code rate is changed according to the channel states. Two channel states having significant effects on the bit error probability are considered: one is the effective number of users considered in Part 1, and the other is the fading environment considered in Part 2. These channel states are estimated based on retransmission requests. The criterion for the change of the code rate is to maximize the throughput under given error bound. Simulation results show that we can transmit maximum amount of information if we change the code rate based on the channel states.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1985년도 하계학술회의논문집
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• pp.254-256
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• 1985

• 대한수학회보
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• 제52권3호
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• pp.809-823
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• 2015

This paper is devoted to presenting a MacWilliams type identity for m-spotty RT weight enumerators of byte error control codes over finite commutative Frobenius rings, which can be used to determine the error-detecting and error-correcting capabilities of a code. This provides the relation between the m-spotty RT weight enumerator of the code and that of the dual code. We conclude the paper by giving three illustrations of the results.

• 한국정보통신학회논문지
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• 제24권9호
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• pp.1180-1186
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• 2020

임베디드 시스템 중 하나인 TPU (Tiny Processing Unit)를 사용하는 데에는 많은 제약들이 따른다. 외부 충격에 의해 데이터 통신 중 잡음이 발생하거나, 충분한 전력이 공급되지 않아 문턱전압을 넘지 못해 올바른 값 전달이 이루어지지 않는 경우가 있다. 이러한 문제점들을 해결하기 위해 많은 임베디드 시스템에서는 ECC (Error Correcting Code)를 사용하는데, ECC를 추가하게 되면서 메모리에서 데이터를 읽어오는 시간이 더 오래 걸리게 되는 문제점이 발생한다. 따라서 우리는 ECC 처리된 코드를 읽어오는 과정을 병렬처리하여 병목현상을 완화하고 TPU의 속도 및 데이터 안정성을 높이는 모델을 제안한다. 제안된 구조는 기존 구조에 비해 메모리를 조금 더 사용하여 안정성과 더 빠른 속도를 보여준다. 실험은 행렬의 연산을 사용하여 진행되었으며, 제안된 구조는 이전의 구조보다 7% 빠른 속도를 보여준다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.273-276
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• 2000

Recently, Turbo code has been considered for channel coding in IMT-2000(International Mobile Telecommunication-2000) system, because it offers better error correcting capability than the traditional convolution/viterbi coding . In this paper, a turbo code decoder for speech transmission in IMT-2000 system with frame size 192 bits, constrait length K=3, generator polynomials G(5,7) and code rate R=1/3 is designed using SOVA(Soft Output Viterbi Algorithm) and block interleaver