전기전자학회논문지 (Journal of IKEEE)

  • 제21권2호
  • /
  • Pages.130-135
  • /
  • 2017
  • /
  • 1226-7244(pISSN)
  • /
  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
권호 표지
DOI QR코드

DOI QR Code

FPGA implementation of overhead reduction algorithm for interspersed redundancy bits using EEDC

  • Kim, Hi-Seok (Dept. of Electronics Engineering, Cheongju University)
  • 투고 : 2017.06.14
  • 심사 : 2017.06.30
  • 발행 : 2017.06.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Normally, in data transmission, extra parity bits are added to the input message which were derived from its input and a pre-defined algorithm. The same algorithm is used by the receiver to check the consistency of the delivered information, to determine if it is corrupted or not. It recovers and compares the received information, to provide matching and correcting the corrupted transmitted bits if there is any. This paper aims the following objectives: to use an alternative error detection-correction method, to lessens both the fixed number of the required redundancy bits 'r' in cyclic redundancy checking (CRC) because of the required polynomial generator and the overhead of interspersing the r in Hamming code. The experimental results were synthesized using Xilinx Virtex-5 FPGA and showed a significant increase in both the transmission rate and detection of random errors. Moreover, this proposal can be a better option for detecting and correcting errors.

키워드

참고문헌

  1. M. Liu, Y. Zhao, and H. Guo, "Research on the Distribution and Self-Similarity Characteristics of End-to-End Network Delay," International Journal of Future Generation Communication and Networking, vol. 8, pp.291-302, June 2015 https://doi.org/10.14257/ijfgcn.2015.8.3.28
  2. I. M. A. D. Suarjaya, "A New Algorithm for Data Compression Optimization," International Journal of Advanced Computer Science and Applications, vol. 3, 2012
  3. J. M. Tang, P. M. Lane, and K. A. Shore, "High-Speed Transmission of Adaptively Modulated Optical OFDM Signals Over Multimode Fibers Using Directly Modulated DFBs," Journal of Lightwave Technology, vol. 24, January 2006
  4. H. Al-Bahadili, "A Novel Lossless Data Compression Scheme Based on the Error Correcting Hamming Codes," Computers and Mathematics with Applications, vol. 56, July 2008
  5. I. R. Irvin, "Cyclic redundancy checks with factorable generators," IEEE Proceedings-Communications, vol. 150, pp. 17-20, February 2003. https://doi.org/10.1049/ip-com:20030189
  6. S. I. Park, and K. C. Yang, "Extended Hamming accumulate codes and modified irregular repeat accumulate codes," Electronics Letters, vol. 10, pp. 467-468, May 2002.
  7. P. Kora, "Single Bit Error Detection and Correction using Novel Hamming Code Method," Imperial Journal of Interdisciplinary Research (IJIR) , vol. 3, 2017.
  8. P. Koopman, and T. Chakravarty, "Cyclic redundancy code (CRC) polynomial selection for embedded networks," Proceedings of The International Conference on Dependable Systems and Networks, 2004
  9. R. T. Murade, M. M. Mujahid, and M. Sabir, "The Design and Implementation of a Programmable Cyclic Redundancy Check(CRC) Computation Circuit Architecture using FPGA," International Journal of Science and Modern Engineering(IJ ISME) , vol. 1, November 2013.
  10. H. Mukhtar, A. Al-Dweik, M. Al-Mualla, "CRC-Free Hybrid ARQ System using Turbo Product Codes," IEEE Transactions on Communications, vol. 62, December 2014.
  11. A. H. Saleh, "Design of Hamming Code for 64-bit Single Error Detection and correction with VHDL," Diyala Journal of Engineering Sciences, vol. 8, September 2015.
  12. H. Wang, "A Kind of Performance Improvement of Hamming Code," Information and Management Engineering, Proceedings of International Conference in ICCIC, September 2011