• Proceedings of the KIEE Conference
• /
• 2005.07b
• /
• pp.1619-1621
• /
• 2005

AC electric railway feeding system classifies into three groups such as normal, TIE and PP feeding method. If the feeding scheme of ac electric railway is changed, current distribution flowing through the line is also modified. And if the current distribution is altered according to the feeding scheme, returned tendency through rail load current or fault current of the train is changed. So the investigation about error correcting method of protective relay is needed considering feeding scheme. In this paper prior to error correcting of protective relay, through interpreting feeding circuit, changes in current distribution of the rail in accordance with feeding would be predicted and analyzed.

• Proceedings of the KIEE Conference
• /
• 1985.07a
• /
• pp.254-256
• /
• 1985

• Proceedings of the Korea Society of Mathematical Education Conference
• /
• 1990.07a
• /
• pp.62-62
• /
• 1990

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.262-265
• /
• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.1C
• /
• pp.8-13
• /
• 2006

A new RS(Reed Solomon) Decoder design method, using Galois Subfield GF($2^4$) Multiplier, is described. The Decoder is designed using Normalized error position stored ROM. Here New Inverse Calculator in GF($2^8$) is designed, which is simpler and faster than the classical GF($2^8$) direct inverse calculator, using the Galois Subfield GF($2^4$) Arithmatic operator.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1986.10a
• /
• pp.79-82
• /
• 1986

For the purpose of error correcting, a concatenated coding system has been proposed by cascading two codes-(7, 3) Reed-Solomon and (2, 1, 6) convolutional codes. As a result of the result of the computer simulation and the experiment, the (98.21) concatenated code has been show to be able to correct 12 randome error and 16 bust errors. When the channel error is about 1.2x10, this system indicats most efficient.

• Journal of the Korean Society of Safety
• /
• v.9 no.4
• /
• pp.42-48
• /
• 1994

A rotor flux error-based approach for correcting the rotor time constant estimation used in the slip frequency calculator of indirect field oriented controller is presented in this paper. The controller was derived from the d-q induction machine model. Slip frequency gain is dependent on the machine parameter errors. And parameter errors result in rotor flux error. Thus, estimated rotor flux is compared to commanded rotor flux. The error between them is used for the estimation of rotor time constant. Simulation results which demonstrate the performance of this approach are presented.

• Proceedings of the Acoustical Society of Korea Conference
• /
• 1991.06a
• /
• pp.78-81
• /
• 1991

Digital radio data is composed of groups which are divided into 4 blocks of 26 bits. And each block is made up of information word and check word. Check word of digital radio data that is composed ofcode word and offset word is used for group/block synchronization and error correction. In this paper, we have investigated the group/block synchronizer using offext word and shortened cyclic decoder for correcting error produced during the radio data transimission. Also, we have simulated the decoding process of the proposed decoder. From the simulation results, we have confirmed that the proposed decoder most with the required coding capcbility.

• The Magazine of the IEIE
• /
• v.11 no.2
• /
• pp.1-11
• /
• 1984

본 지 2월호에서 구술한 선형부호에 이어 이번호에서는 순회부호에 대해 기술하고자 한다. 선형블럭부호중 중요한 부류에 속하는 순회부호(cyclic code)는 그 내용이 대수적 구조를 갖고 있어 부호화 회로는 물론 부호에 필요한 오증(syndrome)계산회로 등 귀환연결이 있는 치환레지스터(shift register)를 사용한 장치화(implementation)가 매우 용이하다는 이점이 있다. 이런 순회부호는 산발오진(random error)뿐 아니라 연집오진(burst error)도 정정할 수 있는 매우 효과적인 부호로서 다중오진정정능력(multiple error correcting capability)을 갖는 BCH부호도 순회부호의 일종이다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.9
• /
• pp.1180-1186
• /
• 2020

One of the Embedded systems Tiny Processing Unit (TPU) usually acts in harsh environments like external shock or insufficient power. In these cases, data could be polluted, and cause critical problems. As a solution to data pollution, many embedded systems are using Error Correcting Code (ECC) to protect and restore data. However, ECC processing in TPU increases the overall processing time by increasing the time of instruction fetch which is the bottleneck. In this paper, we propose an architecture of parallelized ECC block to the reduce bottleneck of TPU. The proposed architecture results in the reduction of time 10% compared to the original model, although memory usage increased slightly. The test is evaluated with a matrix product that has various instructions. TPU with proposed parallelized ECC block shows 7% faster than the original TPU with ECC and was able to perform the proposed test accurately.