1 |
Sunghoon Kwon and Hyunchul Shin, 'Anarea-efficient VLSI architecture of Reed-Solomon decoder/encoder for digital VCRs,' IEEE Transactions on Consumer Eiectronics, Vol. 43, No.4, Nov. 1997
|
2 |
Hyeong-Keon An, '2 Error Correcting RS Decoder design', IDEC Conference Paper, KOEX, October 20-24, 2004
|
3 |
Hyeong-Keon An, TS Joo et ai, 'The New RS Ecc Codec For Digital Audio and Video', IEEE CES Conference paper, PP. 112-115, 1992
|
4 |
Shu Lin, Daniel J. Costello, Jr., 'Error Control Coding,' Prentice-Hall, pp.240-261 (20044)
|
5 |
US patent number 5227992, 'Operational Method and Apparatus over using a Subfield GF ', Man-young Lee, HyeongKeon An et al., 1993 Jul. 13
|
6 |
Lee Man Young, 'BCH coding and Reed-Solomon Coding theory,' 1990, Minumsa (Daewoo Academic Press)
|
7 |
岡野博 : ROM used 2 to 3 error correcting BCH Decoder Improvement, 信學技報. AL 82-56 (1982)
|
8 |
Kwang Y.Liu, ' Architecture for VLSI design of Reed-Solomon Decoders, 'IEEE Transactions on Computers. Vol.33, No.2, Feb. 1984
|