• Korean Journal of Materials Research
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• v.24 no.12
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• pp.682-688
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• 2014

Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.1121-1124
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• 2015

In this paper, we propose and demonstrate an optimal design of wideband pulsed gamma-ray detectors. Pulsed gamma-ray detectors are designed to operate in a dose rate of $1{\times}10^6{\sim}1{\times}10^8rad(Si)/s$. The input parameter was derived based on the energy ratio of pulse gamma-ray spectrum and the time of the energy. The sensor output current was calculated based on the dose rate control circuit. Using the N-type Epi Wafer, the optimum condition detection sensor was designed based on TCAD. The simulation results show that the optimal Epi layer thickness is 45um when applied voltage 3.3V. The doping concentrations are as follows : N-type is an Arsenic as $1{\times}10^{19}/cm^3$, P-type is a Boron as $1{\times}10^{19}/cm^3$ and Epi layer is Phosphorus as $3.4{\times}10^{12}/cm^3$. Pulse gamma-ray detector diameter is the 1.3mm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.4
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• pp.273-279
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• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• Journal of Sensor Science and Technology
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• v.8 no.5
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• pp.421-426
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• 1999

In this paper, we present p-channel GaAs MOSFET having $Al_2O_3$ as gate insulator fabricated on a semi-insulating GaAs substrate, which can be operated in the depletion mode. $1\;{\mu}m$ thick undoped GaAs buffer layer, $4000\;{\AA}$ thick p-type GaAs epi-layer, undoped $500{\AA}$ thick AlAs layer, and $50\;{\AA}$ thick GaAs cap layer were subsequently grown by molecular beam epitaxy(MBE) on (100) oriented semi-insulating GaAs substrate and this wafer was oxidized. AlAs layer was fully oxidized as a $Al_2O_3$ thin film. The I-V, $g_m$, breakdown charateristics of the fabricated GaAs MOSFET showed that wet thermal oxidation of AlAs/GaAs epilayer/S I GaAs was successful in realizing depletion mode p-channel GaAs MOSFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.1
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• pp.223-228
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• 2017

In this paper, we are proposing an optimal design of wideband pulsed type gamma-ray sensors. These sensors were manufactured based on the design results and after word electrical properties were analyzed. The sensor input parameters were derived on the basis of pulsed gamma-ray spectrum and time-dependent energy rate, and the output current which were derived on the basis of the sensor sensitivity control circuit. Pulsed gamma-ray sensors were designed using the TCAD simulators. The design results show that the optimal Epi layer thickness is 45um with the applied voltage 3.3V and the diameter is 2.0mm. The doping concentrations are as follows : N-type is an Arsenic as $1{\times}10^{19}/cm^3$, P-type is a Boron as $1{\times}10^{19}/cm^3$ and Epi layer is Phosphorus as $3.4{\times}10^{12}/cm^3$. The fabricated sensor was a leakage current, 12pA at voltage -3.3V and fully depleted mode at voltage -5V. A test result of pulsed radiation shows that the sensor gives out the optimal photocurrent.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.104-113
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• 1994

We have fabricated n-p-n HBTs using 3-inchAlgaAs/GaAs hetero structure epi-wafers grown by MBE. DC and AC characteristics of HBT devices were measured and analyzed. For HBT epi-structure, Al composition of emitter was graded in the region between emitter cap and emitter. And base layer was designed with concentration of 1${\times}10^{19}/cm^{3}$ and thickness of 50nm, and Be was used as the p-type dopant. Principal processes for device fabrication consist of photolithography using i-line stepper, wet mesa etching, and lift-off of each ohmic metal. The PECVD SiN film was used as the inslator for the metal interconnection. HBT device with emitter size of 3${\times}10{\mu}m^{2}$ resulted in cut-off frequency of 35GHz, maximum oscillation frequency of 21GHz, and current gain of 60. The distribution of the ideality factor of collector and base current was very uniform, and the average values of off-set voltage and current was very uniform, and the average values of off-set voltage and current gain were 0.32V and 32 within a 3-inch wafer.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.941-943
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• 1999

In this paper, the AC breakdown properties to investigate the electrical properties of gate oxide layer in MOSFET was studied. 5 inch arsenic epi-wafer is selected as an experimental specimen, the power MOSFET of a general MOS structure was made. In order to analyze the physical properties of the specimen, the SIMS(secondary ion mass spectroscopy) was used. As the experimental condition, the experiment al of the AC breakdown characteristics was performed when the thickness of gate oxide layer is $600[\AA]$ and $800[\AA]$, the resistivity is $1.2[\Omega{\cdot}cm]$, $1.5[\Omega{\cdot}cm]$ and $1.8[\Omega{\cdot}cm]$, and the diffusion time is 110[min] and 150[min] in temperature $30[^{\circ}C]{\sim}100[^{\circ}C]$. From the analysis result of the SIMS spectrum, it is confirmed that the dielectric strength is decreased by contribution of the impurities ad dition as increasing in thickness of the gate oxide layer in MOSFET.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.463-463
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• 2010

고휘도 고효율 백색 LED (lighting emitting diode)가 차세대 조명광원으로 급부상하고 있다. 백색 LED를 생산하기 위한 공정에서 MOCVD (유기금속화학증착)장비를 이용한 Epi wafer공정은 에피층과 기판의 격자상수 차이와 열팽창계수차이로 인하여 생성되는 에피결함의 제거를 위하여 기판과 GaN 박막층 사이에 완충작용을 해줄 수 있는 버퍼층 (Buffer layer)을 만들고 그 위에 InGaN/GaN MQW (Multi Quantum Well)공정을 하여 고휘도 고효율 백색 LED를 구현할 수 있다. 이 공정에서 기판의 온도가 불균일해지면 wafer 파장 균일도가 나빠지므로 백색 LED의 yield가 떨어진다. 균일한 기판 온도를 갖기 위한 조건으로 기판과 induction heater의 간격, 가스의 흐름, 기판의 회전, 유도가열코일의 디자인 등이 장비의 설계 요소이다. 코일에 교류전류를 흘려주면 이 코일 안 또는 근처에 있는 도전체에 와전류가 유도되어 가열되는 유도가열 방식은 가열 효율이 높아 경제적이고, 온도에 대한 신속한 응답성으로 인하여 열 손실을 줄일 수 있으며, 출력 온도 제어의 용이성 및 배출 가스 등의 오염 없다는 장점이 있다. 본 연구에서는 유도가열방식의 induction heater를 이용하여 회전에 의한 기판의 온도 균일도 측정을 하였다. 기초 실험으로 저항 가열 히터를 통하여 대류에 의한 온도 균일도를 평가하였다. 그 결과 gap이 3 mm일 때, 평균 온도 $166.5^{\circ}C$ 에서 불균일도 6.5 %를 얻었으며 이를 바탕으로 induction heater와 graphite susceptor의 간격이 3 mm일 때, 회전에 의한 온도 균일도를 측정을 하였다. 가열원은 induction heater (viewtong, VT-180C2)를 사용하였고, 가열된 graphite 표면의 온도를 2차원적으로 평가하기 위하여 적외선 열화상 카메라(Fluke, Ti-10)을 이용하여 온도를 측정하였다. 기판을 회전하면서 표면 온도의 평균과 표준 편차를 측정한 결과 2.5 RPM일 때 평균온도 $163^{\circ}C$ 에서 가장 좋은 5.5 %의 불균일도를 확인할 수 있었고, 이를 상용화 전산 유체 역학 코드인 CFD-ACE+의 모델링 결과와 비교 분석 하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.1
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• pp.329-332
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• 2012

LEDs are using widely in a field of illumination, LCD LED backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. To achieve high performance LEDs, one needs to enhance output power, reduce operation voltage, and improve device reliability. In this paper, we have proposed that the optimum design and specialized process could improve the performance of LED chip. It was showed an output power of 7cd and input supplied voltage of 3.2V by the insertion technique of current blocking layer. In this paper, GaN-based LED chip which is built on the sapphire epi-wafer by selective MOCVD were designed and developed. After that, their performances were measured. It showed the output power of 7cd more than conventional GaN-based chip. It will be used the lighting source of a medical equipment and LCD LED TV with GaN-based LED chip.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.1
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• pp.51-56
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• 1981

A new I2L process for a high performance I2L structure is proposed. The modifiedstructure consists of a heavily doped extrinsic base and lowly doped intrinsic base where the collector regions are self-alignment with the intrinsic base regions. The proposed process untilizes spin-on sources as the diffusion sources and the self-alignment of collectors is achieved by using the hardened spin-on source as a diffusion mask. Test devices including a 13-stage ring oscillator have been fabricated by the proposed process on n/n+ silicon wafers with 6.5$\mu$m epitaxial layer. The maximum upward current gain of npn transistors is 8 for a three collector I2L cell. The speed-power product and minimum propagation delay for a one collector structure are 3.5 pJ and 50 ns, respectively.