• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.129-130
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• 2009

The P/E characteristics of $HfO_2$ CTF memory capacitor with $SiO_2/HfO_2/Al_2O_3$(OHA) engineered tunnel barrier were investigated. After a growth of thermal oxide with a thickness of 2 nm, 1 nm $HfO_2$ and 3 $Al_2O_3$ layers were deposited by atomic layer deposition (ALD) system. The band offset was calculated by analysis of conduction mechanisms through Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot. Moreover the PIE characteristics of $HfO_2$ CTF memory capacitor with OHA tunnel barrier was presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.127-128
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• 2008

The electrical characteristics of VARIOT (variable oxide thickness) with various $HfO_2$ thicknesses on thin $SiO_2$ or $Al_2O_3$ layer were investigated. Especially, the charge trapping characteristics of $HfO_2$ layer were intensively studied. The thin $HfO_2$ layer has small charge trapping characteristics while the thick $HfO_2$ layer has large memory window. Therefore, the $HfO_2$ layer is superior material and can be applied to charge storage as well as tunneling barrier of the non-volatile memory applications.

• Nuclear Engineering and Technology
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• v.55 no.11
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• pp.4173-4180
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• 2023

The stability of engineered barriers in high-level radioactive waste disposal systems can be influenced by the decay heat generated by the waste. This study focuses on the thermal analysis of various canister designs to effectively lower the maximum temperature of the engineered barrier. A numerical model was developed and employed to investigate the heat dissipation potential of copper rings placed across the buffer. Various canister designs incorporating copper rings were presented, and numerical analysis was performed to identify the design with the most significant temperature reduction effect. The results confirmed that the temperature of the buffer material was effectively lowered with an increase in the number of copper rings penetrating the buffer. Parametric studies were also conducted to analyze the impact of technical gaps, copper thickness, and collar height on the temperature reduction. The numerical model revealed that the presence of gaps between the components of the engineered barrier significantly increased the buffer temperature. Furthermore, the reduction in buffer temperature varied depending on the location of the gap and collar. The methods proposed in this study for reducing the buffer temperature hold promise for contributing to cost reduction in radioactive waste disposal.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.53-53
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• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.34-34
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• 2009

The electrical characteristics of tunnel barrier engineered charge trap flash (TBE-CTF) memory with $SiO_2/Si_3N_4/SiO_2/Si$ engineered tunnel barrier, $HfO_2$ charge trap layer and $Al_2O_3$ blocking oxide layer (MAHONOS) were investigated. The energy bad diagram was designed by using the quantum-mechanical tunnel model (QM) and then the CTF memory devices were fabricated. As a result, the best thickness combination of MAHONOS is confirmed. Moreover, not enhanced P/E speed (Program: about $10^6$ times) (Erase: about $10^4$ times) but also enhanced retention and endurance characteristics are represented.

• Nuclear Engineering and Technology
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• v.53 no.3
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• pp.1041-1048
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• 2021

An engineered barrier system (EBS) for the disposal of high-level radioactive waste (HLW) is composed of a disposal canister with spent fuel, a buffer material, a gap-filling material, and a backfill material. As the buffer is located in the empty space between the disposal canisters and the surrounding rock mass, it prevents the inflow of groundwater and retards the spill of radionuclides from the disposal canister. Due to the fact that the buffer gradually becomes saturated over a long time period, it is especially important to investigate its thermal-hydro-mechanical-chemical (THMC) properties considering variations of saturated condition. Therefore, this paper suggests a new method of measuring thermal conductivity and water suction for single compacted bentonite at various levels of saturation. This paper also highlights a convenient method of saturating compacted bentonite. The proposed method was verified with a previous method by comparing thermal conductivity and water suction with respect to water content. The relative error between the thermal conductivity and water suction values obtained through the proposed method and the previous method was determined as within 5% for compacted bentonite with a given water content.

• Nuclear Engineering and Technology
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• v.55 no.4
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• pp.1495-1506
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• 2023

For the safe disposal of high-level radioactive waste using Engineered Barrier Systems (EBS), bentonite buffer is used by its high swelling capability and low hydraulic conductivity. When the bentonite buffer is contacted to heated pore water containing ions by radioactive decay, chemical alterations of minerals such as illitization reaction occur. Illitization of bentonite indicates the alteration of expandable smectite into non-expandable illite, which threatens the stability and integrity of EBS. This study intends to provide a thorough review on the information underlying in the illitization of bentonite, by covering basic clay mineralogy, smectite expansion, mechanisms and observation of illitization, and illitization in EBS. Since understanding of smectite illitization is crucial for securing the safety and integrity of nuclear waste disposal systems using bentonite buffer, this thorough review study is expected to provide essential and concise information for the preventive EBS design.

• Nuclear Engineering and Technology
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• v.55 no.3
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• pp.1191-1198
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• 2023

Bentonite buffer material is a critical component in an engineered barrier system (EBS) for disposing high-level radioactive waste (HLW). The bentonite buffer material protects the disposal canister from groundwater penetration and releases decay heat to the surrounding rock mass; thus, it should possess high thermal conductivity, low hydraulic conductivity, and moderate swelling pressure to safely dispose the HLWs. Bentonite clay is a suitable buffer material because it satisfies the safety criteria. Several additives have been suggested as mixtures with bentonite to increase the thermal-hydraulic-mechanical-chemical (THMC) properties of bentonite buffer materials. Therefore, this study investigated the geotechnical, mineralogical, and THMC properties of several candidate additives such as sand, graphite, granite, and SiC powders. Datasets obtained in this study can be used to select adequate additives to improve the THMC properties of the buffer material.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.159-160
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• 2012

지난 30년 동안 플래시 메모리의 주류 역할을 하였던 부유 게이트 플래시 메모리는 40 nm 기술 노드 이하에서 셀간 간섭, 터널 산화막의 누설전류 등에 의한 오동작으로 기술적 한계를 맞게 되었다. 또한 기존의 비휘발성 메모리는 동작 시 높은 전압을 요구하므로 전력소비 측면에서도 취약한 단점이 있다. 그러나 이러한 문제점들을 기존의 Si기반의 소자기술이 아닌 새로운 재료나 공정을 통해서 해결하려는 연구가 최근 활발하게 진행되고 있다. 특히, 플래시 메모리의 중요한 구성요소의 하나인 터널 산화막은 메모리 소자의 크기가 줄어듦에 따라서 SiO2단층 구조로서는 7 nm 이하에서 stress induced leakage current (SILC), 직접 터널링 전류의 증가와 같은 많은 문제점들이 발생한다. 한편, 기존의 부유 게이트 타입의 메모리를 대신할 것으로 기대되는 전하 포획형 메모리는 쓰기/지우기 속도를 향상시킬 수 있으며 소자의 축소화에도 셀간 간섭이 일어나지 않으므로 부유 게이트 플래시 메모리를 대체할 수 있는 기술로 주목받고 있다. 특히, TBM (tunnel barrier engineered memory) 소자는 유전율이 큰 절연막을 적층하여 전계에 대한 터널 산화막의 민감도를 증가시키고, 적층된 물리적 두께의 증가에 의해 메모리의 데이터 유지 특성을 크게 개선시킬 수 있는 기술로 관심이 증가하고 있다. 본 연구에서는 Si3N4/Ta2O5를 적층시킨 staggered구조의 tunnel barrier를 제안하였고, Si기판 위에 tunnel layer로 Si3N4를 Low Pressure Chemical Vapor Deposition (LPCVD) 방법과 Ta2O5를 RF Sputtering 방법으로 각각 3/3 nm 증착한 후 e-beam evaporation을 이용하여 게이트 전극으로 Al을 150 nm 증착하여 MIS- capacitor구조의 메모리 소자를 제작하여 동작 특성을 평가하였다. 또한, Si3N4/Ta2O5 staggered tunnel barrier 형성 후의 후속 열처리에 따른 전기적 특성의 개선효과를 확인하였다.