• Journal of Korean Society of Industrial and Systems Engineering
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• v.38 no.3
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• pp.21-28
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• 2015

As film products are increasingly used in a wide range of areas, from producing traditional flexible packaging to high-tech electronic products, a higher level of quality is demanded. Most film products are made in the form of rolled finished goods, therefore, various quality issues related to their shape characteristics must be addressed. The thickness of the film products is one of the most common and important critical-to-quality attributes (CTQs). Particularly, the degree of thickness uniformity is more important than other thickness parameters, because it will be potential causes of many secondary thickness-related quality problems, such as wrinkles or faulty windings. To control the degree of thickness uniformity, the fixed bending region is oneof the most important CTQs to manage. Fixed bending regions are special points in the transverse direction of a rolled product with consistent minute variations of the thickness gap. This paper describes the measurement and analysis of thickness uniformity data, which were performed in a real manufacturing field of biaxial oriented polypropylene (BOPP) film. In previous researches, quality function deployment (QFD) or fault tree analysis were used to find the most critical process attributes out to controlthe CTQ of thickness uniformity. Whereas, this paper uses traditional control charts to find the most critical process attributes out in this problem. In addition, the selection of one of the major critical process attributes (CTPs) that is expected to affect the CTQ of thickness uniformity is also described. The selected critical-to-process attributes are the controlled temperatures along the transverse direction. A dramatic improvement in thickness uniformity was observed when the selected CTPs were controlled.

• Macromolecular Research
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• v.12 no.1
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• pp.78-84
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• 2004

Advanced epoxy molding compounds (EMCs) should be considered to alleviate the thermal stress problems caused by low thermal conductivity and high elastic modulus of an EMC and by the mismatch of the coefficient of thermal expansion (CTE) between an EMC and the Si-wafer. Though A1N has some advantages, such as high thermal conductivity and mechanical strength, an A1N-filled EMC could not be applied to commercial products because of its low fluidity and high modules. To solve this problem, we used 2-$\mu\textrm{m}$ fused silica, which has low porosity and spherical shape, as a small size filler in the binary mixture of fillers. When the composition of the silica in the binary filler system reached 0.3, the fluidity of EMC was improved more than twofold and the mechanical strength was improved 1.5 times, relative to the 23-$\mu\textrm{m}$ A1N-filled EMC. In addition, the values of the elastic modules and the dielectric constant were reduced to 90％, although the thermal conductivity of EMC was reduced from 4.3 to 2.5 W/m-K, when compared with the 23-$\mu\textrm{m}$ A1N-filled EMC. Thus, the A1N/silica (7/3)-filled EMC effectively meets the requirements of an advanced electronic packaging material for commercial products, such as high thermal conductivity (more than 2 W/m-K), high fluidity, low elastic modules, low dielectric constant, and low CTE.

• Journal of Welding and Joining
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• v.29 no.6
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• pp.65-70
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• 2011

The effect of flip chip bonding parameters on formation of intermetallic compounds (IMCs) between Au stud bumps and Sn-3.5Ag solder was investigated. In this study, flip chip bonding temperature was performed at $260^{\circ}C$ and $300^{\circ}C$ with various bonding times of 5, 10, and 20 sec. AuSn, $AuSn_2$ and $AuSn_4$ IMCs were formed at the interface of joints and (Au, Cu)$_6Sn_5$ IMC was observed near Cu pad side in the joint. At bonding temperature of $260^{\circ}C$, $AuSn_4$ IMC was dominant in the joint compared to other Au-Sn IMCs as bonding time increased. At bonding temperature of $300^{\circ}C$, $AuSn_2$ IMC clusters, which were surrounded by $AuSn_4$ IMC, were observed in the solder joint due to fast diffusivity of Au to molten solder with increased bonding temperature. Bond strength of Au stud bump joined with Sn-3.5Ag solder was about 23 gf/bump and fracture mode of the joint was intergranular fracture between $AuSn_2$ and $AuSn_4$ IMCs regardless bonding conditions.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.411-418
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• 2011

The current study investigates the electroplating characteristics of Sn-Cu eutectic micro-bumps electroplated on a Si chip for flip chip application. Under bump metallization (UBM) layers consisting of Cr, Cu, Ni and Au sequentially from bottom to top with the aim of achieving Sn-Cu bumps $10\times10\times6$ ${\mu}m$ in size, with 20${\mu}m$ pitch. In order to determine optimal plating parameters, the polarization curve, current density and plating time were analyzed. Experimental results showed the equilibrium potential from the Sn-Cu polarization curve is -0.465 V, which is attained when Sn-Cu electro-deposition occurred. The thickness of the electroplated bumps increased with rising current density and plating time up to 20 mA/$cm^2$ and 30 min respectively. The near eutectic composition of the Sn-0.72wt%Cu bump was obtained by plating at 10 mA/$cm^2$ for 20 min, and the bump size at these conditions was $10\times10\times6$ ${\mu}m$. The shear strength of the eutectic Sn-Cu bump was 9.0 gf when the shearing tip height was 50% of the bump height.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.11
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• pp.755-759
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• 2016

The use of heat pipes in the electronic telecommunication field is increasing. Among the various types of heat pipes, the thin flat heat pipe has relatively high applicability compared with the circular heat pipe in the electronic packaging application. The thin flat heat pipe based on extrusion fabrication has a simple capillary wick structure consisting of rectangular cross sectional grooves on the inner wall of the pipe. Although the groove serves as a simple capillary wick, and many such grooves are provided on the inner wall, it is difficult for the grooves to realize a sufficiently high capillary force. In the present study, a thin flat heat pipe with a wire bundle was developed to overcome the drawback of poor capillary force in the thin flat heat pipe with grooves, and was evaluated by conducting tests. In the performance test, the thin flat heat pipe with the wire bundle showed a lower thermal resistance of approximately 3.4 times, and a higher heat transfer rate of approximately 3.8 times with respect to the thin flat heat pipe with grooves as the capillary wick respectively. The possibility of using the wire bundle as a capillary wick in the heat pipe was validated in the present study; further study for commercializing this concept will be taken up in the future.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.6
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• pp.526-534
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• 2011

The MFS (Mlti-Functional Structure) concept, which integrates the electronics, thermal control and structure into a single packaging system, has been developed and applied to reduce the volume and weight of the satellite. Therefore, this MFS can eliminate the bulky chassis/frames, cables and connectors of the electronic equipment. The main point of this traditional MFS is the replacement of the electrical chassis/frames with MCMs (Multi-Chip Modules) that require much costs and efforts for developing. This paper shows the new MFS concept that effectively saves the volume and weight. The structure including the thermal control and radiation shielding elements will be designed and manufactured as the rectangular grid-stiffened structure. The rectangular grid-stiffened structure is the modification of the iso-grid structure, and provides the enough spaces for putting the general PCBs without the chassis/frames.

• Membrane Journal
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• v.27 no.2
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• pp.154-166
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• 2017

Polymeric films for gas barrier applications such as food packaging and electronic devices have attracted great interest due to their cheap, light and easy processability among gas barrier materials. Especially in electronic devices, extremely low gas permeance is necessary for maintaining the device performance. However, current polymeric barrier films still suffer from relatively high gas permeance than other materials. Therefore, there have been strong needs to enhance the gas barrier performance of polymeric barrier films while keep their own advantages. Recently, graphene is highlighted as a 2D-layered material for gas barrier applications. However, owing to the poor workability and difficulty to produce in engineering scale, graphene oxide (GO) is on the rise. GO consists of oxygen-containing functional groups on surface with intrinsic 2D-layered structure and high aspect ratio, and it can be well-dispersed in aqueous polar solvents like water, resulting in scalable mass production. Here, we prepared GO incorporated polyimide (PI) nanocomposites. PI is widely used barrier polymer with high mechanical strength and thermal and chemical stability. We demonstrated that PI/GO nanocomposites could perform as a gas barrier. Furthermore, surfactants (Triton X-100 (TX) and Sodium deoxycholate (SDC)) are introduced to enhance the gas barrier performance by improving the degree of dispersion of GO in PI matrix. As a result, TX enhanced the gas barrier performance of PI/GO nanocomposites which is similar to predicted value. This finding will provide new insight to polymer nanocomposites for gas barrier applications.