• Composites Research
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• v.15 no.1
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• pp.32-40
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• 2002

This study developed fabrication process of $SiC_p/Al$ metal matrix composites as electronic packaging materials by squeeze casting method. The $SiC_p$ preform were fabricated in newly designed preform mold using about 0.8 % of inorganic binder(SiO$_2$) and 5 vol.% of $Al_2O_3$fiber. To infiltrate the molten metal into the preform, fabrication condition such as the temperature and the pressure were selected. Applying the fabrication conditions, heat transfer analysis were preformed using finite element method and thus analyzed the temperature distribution and cooling characteristic during the squeeze casting. For the fabricated composites, impact toughness and thermal expansion coefficient were measured. The metal matrix composites developed in this study have 0.2~0.3 J impact toughness, $8~10 ppm/^{\circ}C$ thermal expansion coefficient and $2.9~3.0g/cm^3$density which is appropriate properties for electronic packaging application.

• Composites Research
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• v.13 no.6
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• pp.23-29
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• 2000

The internal residual stresses within the multilayered structure with sharp interface induced by the difference in thermal expansion coefficient between the materials of adjacent layers often provide the source of failure such as delamination of interfaces etc. Recent development of the multilayered structure with functionally graded interface would be the solution to prevent this kind of failure. However a systematic thermo-mechanical analysis is needed for the customized structural design of multilayered structure. In this study, theoretical model for the thermo-mechanical analysis is developed for multilayered structures of the $Al-SiC_p$ functionally graded composite for electronic packaging. The evolution of curvature and internal stresses in response to temperature variations is presented for the different combinations of geometry. The resultant analytical solutions are used for the optimal design of the multilayered structures with functionally graded interface as well as with sharp interface.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1627-1628
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• 2006

In this paper, mesoporous only platinum electrode and micro pore platinum electrode with mesoporous Pt are fabricated and characterized on a silicon substrate to check their usability as enzymeless sensing electrodes for developing non-disposable glucose sensors integrated with silicon CMOS read out circuitry. Since most of electrochemical glucose sensors are disposable due to the use of the enzymes that are living creatures, these are limited to use in the in-vivo and continuous monitoring system applications. The proposed mesoporous Pt electrode with approximately 2.5nm in pore diameter and 150nm in height was fabricated by using a nonionic surfactant $C_{16}EO_8$ and an electroplating technique. The micro pore Pt electrode with mesoporous Pt means the mesoporous Pt electrode fabricated on top of micro pore arrayed Pt electrode with approximately $10{\mu}m$ in pore diameter and $80{\mu}m$ in height. The measured current responses at 10mM glucose solution of plane Pt, micro pore Pt, micro pore with mesoporus Pt, and mesoporous Pt electrodes are approximately $9.9nA/mm^2$, $92.4nA/mm^2$, $3320nA/mm^2$ and $44620nA/mm^2$, respectively. These data indicate that the mesoporous Pt electrode is much more sensitive than the other Pt electrodes. Thus, it is promising for non-disposable glucose sensor and electrochemical sensor applications.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

• Electronics and Telecommunications Trends
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• v.38 no.6
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• pp.41-51
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• 2023

Heat dissipation technology for semiconductors and electronic packaging has a substantial impact on performance and lifespan, but efficient heat dissipation is currently facing limited improvement. Owing to the high integration density in electronic packaging, heat dissipation components must become thinner and increase their performance. Therefore, heat dissipation materials are being devised considering conductive heat transfer, carbon-based directional thermal conductivity improvements, functional heat dissipation composite materials with added fillers, and liquid-metal thermal interface materials. Additionally, in heat dissipation structure design, 3D printing-based complex heat dissipation fins, packages that expand the heat dissipation area, chip embedded structures that minimize contact thermal resistance, differential scanning calorimetry structures, and through-silicon-via technologies and their replacement technologies are being actively developed. Regarding dry cooling using single-phase and phase-change heat transfer, technologies for improving the vapor chamber performance and structural diversification are being investigated along with the miniaturization of heat pipes and high-performance capillary wicks. Meanwhile, in wet cooling with high heat flux, technologies for designing and manufacturing miniaturized flow paths, heat dissipating materials within flow paths, increasing heat dissipation area, and reducing pressure drops are being developed. We also analyze the development of direct cooling and immersion cooling technologies, which are gradually expanding to achieve near-junction cooling.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.3 s.32
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• pp.55-62
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• 2004

The oxidation of pure Sn and high Pb-Sn alloys was investigated under different oxidizing conditions of temperature and humidity. Both the chemical nature and the amount of oxides were characterized using electrochemical reduction analysis by measuring the electrolytic reduction potential and total transferred electrical charges. For pure tin, SnO grew faster under humid condition than in dry air at $85^{\circ}C$. A very thin (<10 ${\AA}$) layer of SnO, was formed on the top surface under humid condition. The mixture of SnO and $SnO_2$ was found for oxidation at $150^{\circ}C$. XPS and AES were performed to support the result of oxide reduction.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.33-37
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• 2008

A noticeable amount of Kirkendall voids formed at the Sn-3.5Ag solder joint with electroplated Cu, and that became even more significant when an additive was added to Cu electroplating bath. With SPS, a large amount of voids formed at the $Cu/Cu_3Sn$ interface of the solder joint during thermal aging at $150^{\circ}C$. The in-situ AES analysis of fractured joints revealed S segregation on the void surface. Only Cu, Sn, and S peaks were detected at the fractured $Cu/Cu_3Sn$ interfaces, and the S peak decreased rapidly with AES depth profiling. The segregation of S at the $Cu/Cu_3Sn$ interface lowered interface energy and thereby reduced the free energy barrier for the Kirkendall void nucleation. The drop impact test revealed that the electrodeposited Cu film with SPS degraded drastically with aging time. Fracture occurred at the $Cu/Cu_3Sn$ interface where a lot of voids existed. Therefore, voids occupied at the $Cu/Cu_3Sn$ interface are shown to seriously degrade drop reliability of solder joints.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.25-33
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• 2001

Sn-3.5Ag-xBi alloys with five different levels of Bi (0, 2.5, 4.8, 7.5, 10 wt%) were prepared for evaluating creep properties. Cast alloys were roiled and heat treated to provide stable microstructures during the subsequent creep tests, which were conducted under constant load using dog-bone specimens. For the Bi containing alloys, creep strength showed the maximum around 2.5 wt%Bi and tended to decrease with increasing Bi content. The stress exponent of the alloy was around 4, suggesting typical dislocation creep, but the exponent was 2 for the 10 wt%Bi alloy, suggesting creep assisted by grain boundary Sliding. For the Bi containing alloys, the brittle fracture mode appeared showing small amount of reduction of area, while the ductile fracture mode was true for the Bi free alloy. Microstructural examination of ruptured specimens showed cavitations on grain boundaries normal to the load axis, and a significant of grain boundary sliding for the Bi containing alloys.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.04a
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• pp.193-197
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• 2003

As one of the core technologies in the field of the optical communication with WDM, the optical cross connector with movements of micro mirrors is getting important day by day. The packaging structure of 2-dimensional NxN MOEMS switch should be determined by the harmonization of the following items such as the geometrical compatability between optical and structural components, the characteristics of optical input and output parts with device, and the electrical performance for the operation of micro mirrors. Therefore, the packaging process could be defined as the integrated technology completed by the optical and electrical science and the material science for the understanding of its thermo-mechanical properties with packaging materials. In the present study, the harmonization between the optical and structural components as well as the optical characteristics of lens system used will be investigated.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.35-41
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• 2022

In the era of Fifth-Generation (5G), technology requirements such as Artificial Intelligence (AI), Cloud computing, automatic vehicles, and smart manufacturing are increasing. For high efficiency of electronic devices, research on high-intensity circuits and packaging for miniaturized electronic components is important. A solder paste which consists of small solder powders is one of common solder for high density packaging, whereas an electroplated solder has limitation of uniformity of bump composition. Researches are underway to improve wettability through the addition of nanoparticles into a solder paste or the surface finish of a substrate, and to suppress the formation of IMC growth at the metal pad interface. This paper describes the principles of improving the wettability of solder paste and suppressing interfacial IMC growth by addition of nanoparticles.