• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제28권6호
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• pp.371-374
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• 2015

This paper suggests a high performance lateral super barrier rectifier (Lateral SBR) device which has the advantages of both Schottky diode and pn junction, that is, low forward voltage and low leakage current, respectively. Advantage of the proposed lateral SBR is that it can be easily implemented and integrated in current BCD platform. As a result of simulation using TCAD, BVdss = 48 V, $V_F=0.38V$ @ $I_F=35mA$, T_j = $150^{\circ}C$ were obtained with very low leakage current characteristic of 3.25 uA.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.937-940
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• 2005

In this paper, the design of high current and high performance Regulatior IC using BCD Technology are presented. We design the 5A class regulator IC including the VDMOS Pass Tr. of N-sink array structure. Also, to obtain the high current and low power characteristics, the PMOS and BJT device are adapted for the Pass Tr. It is shown that simulation results of Regulator IC with VDMOS Pass Tr. have the Iout=4.5092A, LDO=7.3mV.

• Journal of international Conference on Electrical Machines and Systems
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• 제3권4호
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• pp.451-457
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• 2014

Parallel operation systems have an advantage in that they can be constructed quickly and inexpensively by combining existing electric power converters. However, in this case, there is a peculiar problem in that a cross current flows between the electric power converters. To design a control system more simply and commonalize the core of combination reactors, we reviewed a system construction method for parallel operation systems constructed with three electric power converters.

• Proceedings of the KIPE Conference
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.98-103
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• 2001

In case that electronic ballast employing a valley-fill passive power factor correction (PFC) circuit is used for feeding fluorescent lamps, a new method to reduce crest factor of the lamp current is studied in this paper. In order to reduce crest factor to lower value, a pulse frequency modulation technique based on the waveform of the dc-link voltage which is predetermined by the passive PFC circuit, is taken into the switching control action of the electronic ballast. An equation-based analysis between the crest factor of lamp current and the effect of varying the inverter switching frequency is comprehensively performed.

• Proceedings of the KIEE Conference
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2795-2797
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• Journal of Power Electronics
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• 제12권3호
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• pp.429-438
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• 2012

This paper presents the use of a novel, single-stage high-power-factor electronic ballast with a symmetrical class-DE low-$d{\upsilon}$/$dt$ resonant rectifier as a power-factor corrector for fluorescent lamps. The power-factor correction is achieved by using a bridge rectifier to utilize the function of a symmetrical class-DE resonant rectifier. By employing this topology, the peak and ripple values of the input current are reduced, allowing for a reduced filter inductor volume of the EMI filter. Since the conduction angle of the bridge rectifier diode current was increased, a low-line current harmonic and a power factor near unity can be obtained. A prototype ballast, operating at an 84-kHz fixed frequency and a 220-$V_{rms}$, 50-Hz line input voltage, was utilized to drive a T8-36W fluorescent lamp. Experimental results are presented which verify the theoretical analysis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.185-185
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• 2008

This paper describes the broadband SDC (Single-ended to Differential Converter) for Digital Video Broadcasting-Satellite $2^{nd}$ edition (DVB-S2) receiver tuner IC. It is fabricated by using $0.18{\mu}m$ CMOS process. In order to obtain high linearity and low phase mismatch, the broadband SDC (Single-ended to Differential Converter) is designed with current mirror structure and cross-coupled capacitor and current source binding differential structure at VDD. The simulation result of SDC shows IIP3 of 11.9 dBm and IIP2 of 38 dBm. It consumes 5mA current with 2.7V supply voltage.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.949-952
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• 2000

A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.107-110
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• 2003

In this paper, We introduced that the method for determing the dielectric relaxation time $\tau$ of floating monolayers on water interface. Displacement current flowing across monolayers is analyzed using a rod-like molecular model. It is revealed that the dielectric relaxation time $\tau$of monolayers in the isotropic polar orientational phase is determined using a linear relationship between the monolayer compression speed $\alpha$ and the molecular area Am. here Displacement current gives a peak at A = Am. The dielectric relaxation time $\tau$ of organic monolayers was examined on the basis of the analysis developed here.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.205-205
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• 2007

The SiOC film of carbon centered system was prepared using bistrimethylsilylmethane and oxygen mixed precursor by the chemical vapor deposition. The chemical properties of the SiOC film were analyzed by the I-V measurement and FTIR spectra. The main bond of 950~1200 cm-1 was composed of the Si-C, Si-O-C and Si-O bonds. The leakage current of the SiOC film increased with the increasing of the carbon content, and the drift of the current was similar to the Si-O-C bond content.