• 마이크로전자및패키징학회지
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• 제12권1호
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• pp.77-85
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• 2005

Impedance spectroscopy was applied to low temperature polycrystalline Si in order to investigate the electrical/dielectric information in polycrystalline Si. By combined microstructure and impedance spectroscopy works, it was shown that the electrical information is sensitive to the corresponding microstructure, i.e., the grain size and distribution, judged from the capacitance vs. grain size relationship. At $360 mJ/cm^2$, the maximum in capacitance and the minimum in resistance correspond to the largest grain sizes of unimodal distribution in polycrystalline Si. The electrical/dielectric characterization is compared with Raman spectroscopic characterizations in terms of microstructure.

• 마이크로전자및패키징학회지
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• 제9권3호
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• pp.1-6
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• 2002

A low temperature process technology of copper thin films has been developed by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $130^{\circ}C$ and $250^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5 \times10^{-6}$ Torr vacuum condition and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.0 $\mu \Omega \cdot \textrm{cm}$ was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nano-structures of the copper grains, but more depended on the contamination of the copper films.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1272-1273
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• 2009

We demonstrate conformal phosphor coating and patterning methods on light emitting diodes (LEDs) using image processing based optofluidic maskless lithography (IP-OFML) system in microfluidic channels. IP-OFML allows a real-time detection and dynamic mask generation for packaging of randomly dispersed microchips. Our system detects each chip by considering rotation of the chip through image processing regardless of their arrangement error. Therefore, it precisely packages the chip making conformal polymer layer.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.7-38
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• 2000

Performance, reliability, form factor drive flip chip use. BGAs and CSPs will provide stepping stone to FC DCA .Growing vendor infrastructure - Low cost, high density organic substrates -New generations of fluxes and underfills .Adhesives flip chip technology as a low cost flip chip alternatives -Low cost Au stud or Electroless Ni bumps -Reliable thermal cycling and electrical performance.

• 마이크로전자및패키징학회지
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• 제22권1호
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• pp.1-5
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• 2015

Recently, data throughput of smart electric devices increases dramatically. There is a great interest in a new technology which exceeds the limit of electrical transmission method. Optical PCB can supplement the weakness of electrical signal processing, the research for optical PCB is very active. In this paper, we propose the thermal imprint lithography process to fabrication optical layer of optical PCB and experiment to optimize the process conditions. We confirm process time, pressure, process temperature, demolding temperature and fabricate optical interconnection structure which has $45^{\circ}$ tilted mirror surface for confirm the interconnection efficiency.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권9호
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• pp.656-661
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• 1999

As a fundamental study for FED tubeless packaging, sodalime-sodalime electrostatic bonding was performed by using on the developed bonding mechanism. Thebonding properties of the bonded sodalime-sodalime structure were investigated through SEM and SIMS analyses. Mo-tip FEA was vacuum-packaged by the developed bonding process and the packaged device generated the field emission current.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 추계학술대회 논문집
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• pp.417-418
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• 2008

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 디스플레이 광소자분야
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• pp.193-197
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• 2003

As one of the core technologies in the field of the optical communication with WDM, the optical cross connector with movements of micro mirrors is getting important day by day. The packaging structure of 2-dimensional NxN MOEMS switch should be determined by the harmonization of the following items such as the geometrical compatability between optical and structural components, the characteristics of optical input and output parts with device, and the electrical performance for the operation of micro mirrors. Therefore, the packaging process could be defined as the integrated technology completed by the optical and electrical science and the material science for the understanding of its thermo-mechanical properties with packaging materials. In the present study, the harmonization between the optical and structural components as well as the optical characteristics of lens system used will be investigated.

• 마이크로전자및패키징학회지
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• 제22권4호
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• pp.15-23
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• 2015

Lead-free bonding has attracted significant attention for automotive power device packaging due to the upcoming environmental regulations. Silver (Ag) is one of the prime candidates for alternative of high Pb soldering owing to its superior electrical and thermal conductivity, low temperature sinterability, and high melting temperature after bonding. In this paper, the bonding technology by Ag paste was introduced. We classified into two Ag paste bonding according to applied pressure, and each bonding described in detail including recent studies.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1551_1552
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• 2009

In this paper, we presented the packaging technologies of CMOS ISFET(Ion Sensitive Field Effect Transistor) pH sensor using post-CMOS process and MCP(Multi Chip Packaging). We have proposed and developed two types of packaging technology. one is one chip, which sensing layer is deposited on the gate metal of standard CMOS ISFET, the other is two chip type, which sensing layer is separated from CMOS ISFET and connected by bonding wire. These proposed packaging technologies would make it easy to fabricate CMOS ISFET pH sensor and to make variety types of pH sensor.