• Title/Summary/Keyword: dynamic element matching

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Comparison of Dynamic Elements Matching Method in the Delta-Sigma Modulators (Dynamic Element Matching을 통한 Multi-bit Delta-Sigma Modulator에서의 DAC Error 감소 방안 비교)

  • Hyun, Deok-Hwan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.1
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    • pp.104-110
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    • 2006
  • The advantage of the DSM which employ multi-bit quantizer is the increased SNR at the modulator's output. Typically 6 dB improvement is effected for every one additional bit. But multi-bit quantizer evidently requires multi-bit DAC in the feedback loop. The integral linearity error of the feedback DAC has direct impact upon the system performance and degraded SNR of the system. In order to mitigate the negative impact the DAC has on the system performance, many DEM(Dynamic Element Matching) schemes has been proposed. Among the proposed schemes, four schemes(DER,CLA,ILA,DWA) are explained and its performance has been compared. DWA(Data Weighted Averaging) method shows the best performance of the all.

A Study on Sigma Delta ADC using Dynamic Element Matching (Dynamic Element Matching을 적용한 Sigma Delta ADC에 관한 연구)

  • Kim, Hwa-Young;Ryu, Jang-Woo;Lee, Young-Hee;Sung, Man-Young;Kim, Gyu-Tae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07b
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    • pp.1222-1225
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    • 2004
  • This paper presents multibit Sigma-Delta ADC using noise-shaped dynamic element matching(DEM). 5-bit flash ADC for multibit quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. The DEM algorithm is implemented in such a way as to minimize additional delay within the feedback loop of the modulator Using this algorithm, distortion spectra from DAC linearity errors are shaped. Sigma Delta ADC achieves 82dB signal to noise ratio over 615H7z bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is designed to use 0.25um CMOS technology with 2.5V supply voltage and verified by HSPICE simulation.

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Efficient Vibration Simulation Using Model Order Reduction (모델차수축소법을 이용한 효율적인 진동해석)

  • Han Jeong-Sam
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.30 no.3 s.246
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    • pp.310-317
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    • 2006
  • Currently most practical vibration and structural problems in automotive suspensions require the use of the finite element method to obtain their structural responses. When the finite element model has a very large number of degrees of freedom the harmonic and dynamic analyses are computationally too expensive to repeat within a feasible design process time. To alleviate the computational difficulty, this paper presents a moment-matching based model order reduction (MOR) which reduces the number of degrees of freedom of the original finite element model and speeds up the necessary simulations with the reduced-size models. The moment-matching model reduction via the Arnoldi process is performed directly to ANSYS finite element models by software mor4ansys. Among automotive suspension components, a knuckle is taken as an example to demonstrate the advantages of this approach for vibration simulation. The frequency and transient dynamic responses by the MOR are compared with those by the mode superposition method.

A 2.5 V 109 dB DR ΔΣ ADC for Audio Application

  • Noh, Gwang-Yol;Ahn, Gil-Cho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.4
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    • pp.276-281
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    • 2010
  • A 2.5 V feed-forward second-order deltasigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-toanalog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analogto-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 $mm^2$ and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply.

A $3^{rd}$ order 3-bit Sigma-Delta Modulator with Improved DWA Structure (개선된 DWA 구조를 갖는 3차 3-비트 SC Sigma-Delta Modulator)

  • Kim, Dong-Gyun;Cho, Seong-Ik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.5
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    • pp.18-24
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    • 2011
  • In multibit Sigma-Delta Modulator, one of the DEM(Dynamic Element Matching) techniques which is DWA(Data Weighted Averaging) is widely used to get rid of non-linearity caused by mismatching of capacitor that is unit element of feedback DAC. In this paper, by adjusting clock timing used in existing DWA architecture, 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. After designing the 3rd 3-bit SC(Switched Capacitor) Sigma-Delta Modulator by using the proposed DWA architecture, 0.1% of mismatching into unit element in input frequency 20 kHz and sampling frequency 2.56 MHz. As a consequence of the simulation, It was able to get the same resolution as the existing architecture and was able to reduce the number of MOS Tr. by 222.

The DWA Design with Improved Structure by Clock Timing Control (클록 타이밍 조정에 의한 개선된 구조를 가지는 DWA 설계)

  • Kim, Dong-Gyun;Shin, Hong-Gyu;Cho, Seong-Ik
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.59 no.4
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    • pp.401-404
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    • 2010
  • In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

Clustering of Stereo Matching Data for Vehicle Segmentation (차량분리를 위한 스테레오매칭 데이터의 클러스터링)

  • Lee, Ki-Yong;Lee, Joon-Woong
    • Journal of Institute of Control, Robotics and Systems
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    • v.16 no.8
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    • pp.744-750
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    • 2010
  • To segment instances of vehicle classes in a sparse stereo-matching data set, this paper presents an algorithm for clustering based on DP (Dynamic Programming). The algorithm is agglomerative: it begins with each element in the set as a separate cluster and merges them into successively larger clusters according to similarity of two clusters. Here, similarity is formulated as a cost function of DP. The proposed algorithm is proven to be effective by experiments performed on various images acquired by a moving vehicle.

Dynamic Analysis of Rotating Bodies Using Model Order Reduction (모델차수축소기법을 이용한 회전체의 동해석)

  • Han, Jeong-Sam
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2011.04a
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    • pp.443-444
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    • 2011
  • This paper discusses a model order reduction for large order rotor dynamics systems results from the finite element discretization. Typical rotor systems consist of a rotor, built-on parts, and a support system, and require prudent consideration in their dynamic analysis models because they include unsymmetric stiffness, localized nonproportional damping and frequency dependent gyroscopic effects. When the finite element model has a very large number of degrees of freedom because of complex geometry, repeated dynamic analyses to investigate the critical speeds, stability, and unbalanced response are computationally very expensive to finish within a practical design cycle. In this paper, the Krylov-based model order reduction via moment matching significantly speeds up the dynamic analyses necessary to check eigenvalues and critical speeds of a Nelson-Vaugh rotor system. With this approach the dynamic simulation is efficiently repeated via a reduced system by changing a running rotational speed because it can be preserved as a parameter in the process of model reduction. The Campbell diagram by the reduced system shows very good agreement with that of the original system. A 3-D finite element model of the Nelson-Vaugh rotor system is taken as a numerical example to demonstrate the advantages of this model reduction for rotor dynamic simulation.

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A Multiphase Compensation Method with Dynamic Element Matching Technique in Σ-Δ Fractional-N Frequency Synthesizers

  • Chen, Zuow-Zun;Lee, Tai-Cheng
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.3
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    • pp.179-192
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    • 2008
  • A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

Eigenvalue and Frequency Response Analyses of a Hard Disk Drive Actuator Using Reduced Finite Element Models (축소된 유한요소모델을 이용한 하드디스크 구동부의 고유치 및 주파수응답 해석)

  • Han, Jeong-Sam
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.31 no.5
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    • pp.541-549
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    • 2007
  • In the case of control for mechanical systems, it is highly useful to be able to provide a compact model of the mechanical system to control engineers using the smallest number of state variables, while still providing an accurate model. The reduced mechanical model can then be inserted into the complete system models and used for extended system-level dynamic simulation. In this paper, moment-matching based model order reductions (MOR) using Krylov subspaces, which reduce the number of degrees of freedom of an original finite element model via the Arnoldi process, are presented to study the eigenvalue and frequency response problems of a HDD actuator and suspension system.