• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.183-195
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• 2012

We propose a variable-latency Decimal Floating Point(DFP) adder which adopts the dual data path scheme. It is to speed addition and subtraction of operand that has identical exponents. The proposed DFP adder makes use of L. K. Wang's operand alignment algorithm, but operates through high speed data-path in guaranteed accuracy range. Synthesis results show that the area of the proposed DFP adder is increased by 8.26% compared to the L. K. Wang's DFP adder, though critical path delay is reduced by 10.54%. It also operates at 13.65% reduced path than critical path in case of an operation which has two DFP operands with identical exponents. We prove that the proposed DFP adder shows higher efficiency than L. K. Wang's DFP adder when the ratio of identical exponents is larger than 2%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.384-389
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• 2003

A new two-step soft-output Viterbi algorithm (SOVA) decoder architecture is presented. A significant reduction in the decoding latency can be achieved through the use of the dual-port RAM in the survivor memory structure of the trace-back unit. The system complexity can be lowered due to the determination of the absolute value of the path metric differences inside the add-compare-select (ACS) unit. The proposed SOVA architecture was verified successfully by the functional simulation of Verilog HDL modeling and the FPGA prototyping. The SOVA decoder achieves a data rate very close to that of the conventional Viterbi Algorithm (VA) decoder and the resource consumption of the realized SOVA decoder is only one and a half times larger than that of the conventional VA decoder.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.75-82
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• 2006

In this paper, a space-frequency coded orthogonal frequency division multiplexing (SFC-OFDM) scheme with dual Viterbi decoder is proposed and analyzed. Here, two independent half-rate OFDM symbols are generated after convolutional coding of the binary source code. A dual Viterbi decoder is exploited to decode the demodulated sequences independently in the receiver, and their path metrics are compared. Accordingly, the recovered binary data in the proposed scheme are composed of the combination of the sequences having larger path metrics while those in a conventional system are simply the output of single Viterbi decoder. As a result, the proposed SFC-OFDM scheme has a better performance than the conventional one for all signal-to-noise power ratio.

• The Journal of Korea Robotics Society
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• v.16 no.2
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• pp.137-146
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• 2021

When controlling manipulator, degree of freedom is lost in singularity so specific joint velocity does not propagate to the end effector. In addition, control problem occurs because jacobian inverse matrix can not be calculated. To avoid singularity, we apply Deep Deterministic Policy Gradient(DDPG), algorithm of reinforcement learning that rewards behavior according to actions then determines high-reward actions in simulation. DDPG uses off-policy that uses 𝝐-greedy policy for selecting action of current time step and greed policy for the next step. In the simulation, learning is given by negative reward when moving near singulairty, and positive reward when moving away from the singularity and moving to target point. The reward equation consists of distance to target point and singularity, manipulability, and arrival flag. Dual arm manipulators hold long rod at the same time and conduct experiments to avoid singularity by simulated path. In the learning process, if object to be avoided is set as a space rather than point, it is expected that avoidance of obstacles will be possible in future research.

• Journal of the Korean Statistical Society
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• v.21 no.2
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• pp.201-207
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• 1992

The algorithm for obtaining the isotonic regression in simple tree order, the most basic and simplest model next to the simple order, is considered. We propose to call it "Pool-the-Maximum-Violators" algorithm (PMVA) in conjunction with the "Pool-Adjacent-Violators" algorithm (PAVA) in the simple order. The dual problem of obtaining the isotonic regression in simple tree order is our main concern. An intuitively appealing relation between the primal and the dual problems is demonstrated. The interesting difference is that in simple order the required number of pooling is at least the number of initial violating pairs and any path leads to the solution, whereas in the simple tree order it is at most the number of initial violators and there is only one advisable path although there may be some others leading to the same solution.o the same solution.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.379-388
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• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.200-209
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• 2008

This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.

• Journal of the Korea Institute of Military Science and Technology
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• v.10 no.2
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• pp.107-114
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• 2007

This paper describes the Petri Net(PN) model for reliability analysis of fault-tolerant dual Ethernet which Is applied in Naval Combat System. The network for Naval Combat System performs failure detection and auto path recovery by handling redundant path in case of temporary link failure. After studying the behavior of this kind of network, the reliability analysis model is proposed using stochastic Petri Net and continuous-time Markov chains. Finally, the numerical result is analyzed according to changing the failure rate and the recover rate of link.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2002.04a
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• pp.184-189
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• 2002

Collision free task planning for dual-arm robot which perform many subtasks in a common work space can be achieved in two steps : path planning and trajectory planning. Path planning finds the order of tasks for each robot to minimize path lengths as well as to avoid collision with static obstacles. A trajectory planning strategy is to let each robot move along its path as fast as possible and delay one robot at its initial position or reduce speed at the middle of its path to avoid collision with the other robot.

• Bulletin of the Korean Mathematical Society
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• v.46 no.3
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• pp.521-534
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• 2009

In this paper we present new large-update primal-dual interior point algorithms for $P_*$ linear complementarity problems(LAPS) based on a class of kernel functions, ${\psi}(t)={\frac{t^{p+1}-1}{p+1}}+{\frac{1}{\sigma}}(e^{{\sigma}(1-t)}-1)$, p $\in$ [0, 1], ${\sigma}{\geq}1$. It is the first to use this class of kernel functions in the complexity analysis of interior point method(IPM) for $P_*$ LAPS. We showed that if a strictly feasible starting point is available, then new large-update primal-dual interior point algorithms for $P_*$ LAPS have $O((1+2+\kappa)n^{{\frac{1}{p+1}}}lognlog{\frac{n}{\varepsilon}})$ complexity bound. When p = 1, we have $O((1+2\kappa)\sqrt{n}lognlog\frac{n}{\varepsilon})$ complexity which is so far the best known complexity for large-update methods.