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Design of a High Performance Two-Step SOVA Decoder  

전덕수 (강릉대학교 정보전자공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.7, no.3, 2003 , pp. 384-389 More about this Journal
Abstract
A new two-step soft-output Viterbi algorithm (SOVA) decoder architecture is presented. A significant reduction in the decoding latency can be achieved through the use of the dual-port RAM in the survivor memory structure of the trace-back unit. The system complexity can be lowered due to the determination of the absolute value of the path metric differences inside the add-compare-select (ACS) unit. The proposed SOVA architecture was verified successfully by the functional simulation of Verilog HDL modeling and the FPGA prototyping. The SOVA decoder achieves a data rate very close to that of the conventional Viterbi Algorithm (VA) decoder and the resource consumption of the realized SOVA decoder is only one and a half times larger than that of the conventional VA decoder.
Keywords
SOVA; dual-port RAM;
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