• Title/Summary/Keyword: dual inverter

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An Advanced Dead-Time Compensation Method for Dual Inverter with a Floating Capacitor (플로팅 커패시터를 갖는 이중 인버터를 위한 향상된 데드 타임 보상 기법)

  • Kang, Ho Hyun;Jang, Sung-Jin;Lee, Hyung-Woo;Hwang, Jun-Ho;Lee, Kyo-Beum
    • Journal of IKEEE
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    • v.26 no.2
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    • pp.271-279
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    • 2022
  • This paper proposes an advanced dead-time compensation method for dual inverter with a floating capacitor. The dual inverter with floating capacitor is composed of double two-level inverters and a bulk electrolytic capacitor. The output voltage of the dual inverter is dropped by the conduction voltage of the power semiconductors. The voltage drop and dead-time cause the fundamental and harmonic distortions of output currents. When supplied power for OEW-load is low, the dual inverter operates as single inverter for effective operation. The dead-time compensation method for the dual inverter operated as single inverter is needed for reliability. The proposed method using band pass filter in this paper compensates dead-time, dead-time error and changed voltage drop error of power semiconductors for the dual inverter and dual inverter operated as single inverter. The effectiveness of the proposed method is verified by simulation results.

High Efficiency Drive of Dual Inverter Driven SPMSM with Parallel Split Stator

  • Lee, Yongjae;Ha, Jung-Ik
    • Journal of international Conference on Electrical Machines and Systems
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    • v.2 no.2
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    • pp.216-224
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    • 2013
  • This paper describes dual inverter drive for a fractional-slot concentrated winding permanent magnet synchronous machine (PMSM). PMSMs are widely used in many applications from small servo motors to few megawatts generators thanks to its high efficiency and torque density. Especially, fractional-slot concentrated winding PMSM is very popular in the applications where wide operation range is required because it shows very wide constant power speed ratios. High speed operation, however, requires lots of negative daxis current for reducing back-EMF regardless of output torque. Field weakening current does not contribute to the torque generation in surface mounted PMSM case and causes inverter and copper loss. To reduce the losses from field weakening current, this paper proposes PMSM with split stator and parallel dual inverter drive. Proposed parallel dual inverter drive reduces back-EMF and enables efficient drive at high speed and light load situation. Control strategy of proposed dual inverter system is established through loss analysis and simulation. Proposed concept is verified with practical experiment.

Flux Weakening Control for Surface Mounted Permanent Magnet Synchronous Machine Driven by Dual Inverter (이중 인버터를 이용한 표면 부착형 영구자석 동기전동기의 약자속 제어)

  • Kim, Youngnam;Lee, Yongjae;Ha, Jung-Ik
    • The Transactions of the Korean Institute of Power Electronics
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    • v.18 no.5
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    • pp.437-442
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    • 2013
  • For open-end permanent magnet synchronous machine(PMSM) with dual inverter system, where one inverter is connected to the source and the other is flying, the dc link voltage of the flying inverter can be boosted through the machine. For this reason, when compared with single inverter drive system, higher voltage can be applied to PMSM, and higher torque can be generated in the flux weakening region. In this case, however, active and reactive powers are separately supplied by each inverter to maintain the dc link voltage of flying inverter. Therefore, the required flux weakening control is different from the conventional method for a single inverter drive system. This paper proposes the novel flux weakening control method which maximizes the active voltage component in a dual inverter PMSM drive system. The proposed method was demonstrated and verified through experimental results.

A Novel Five-Level Flying-Capacitor Dual Buck Inverter

  • Liu, Miao;Hong, Feng;Wang, Cheng-Hua
    • Journal of Power Electronics
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    • v.16 no.1
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    • pp.133-141
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    • 2016
  • This paper focuses on the development of a Five-Level Flying-Capacitor Dual Buck Inverter (FLFCDBI) based on the main circuit of dual buck inverters. This topology has been described as not having any shoot-through problems, no body-diode reverse recovery problems and the half-cycle work mode found in the traditional Multi-Level Flying-Capacitor Inverter (MLFCI). It has been shown that the flying-capacitor voltages of this inverter can be regulated by the redundant state selection within one pole. The voltage balance of the flying-capacitors can be achieved by charging or discharging in the positive (negative) half cycles by choosing the proper logical algorithms. This system has a simple structure but demonstrates improved performance and reliability. The validity of this inverter is conformed through computer-aided simulation and experimental investigations.

Selective Dual Duty Cycle Controlled High Frequency Inverter Using a Resonant Capacitor in Parallel with an Auxiliary Reverse Blocking Switch

  • Saha, Bishwajit;Suh, Ki-Young;Kwon, Soon-Kurl;Mishima, Tomokazu;Nakaoka, Mutsuo
    • Journal of Power Electronics
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    • v.7 no.2
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    • pp.118-123
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    • 2007
  • This paper presents a new ZCS-PWM high frequency inverter. Zero current switching operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. Dual duty cycle control scheme is used to provide a wide range of high frequency AC output power regulation that is important in many high frequency inverter applications. It found that a complete soft switching operation can be achieved even for low power setting ranges by introducing high-frequency dual duty cycle control scheme. The proposed high frequency inverter is more suitable for consumer induction heating(IH) applications. The operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

A Passive Lossless Soft-Switching Single Inductor Dual Buck Full-Bridge Inverter

  • Hong, Feng;Wu, Yu;Ye, Zunjing;Ji, Baojian;Zhou, Yufei
    • Journal of Power Electronics
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    • v.18 no.2
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    • pp.364-374
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    • 2018
  • A novel passive lossless soft-switching single inductor dual buck full-bridge inverter (PLSSIDBFBI) is presented in this paper. To accomplish this, a passive lossless snubber circuit is added to a dual buck full-bridge inverter. Therefore, the advantages of the dual buck full-bridge inverter are included in the proposed inverter, and the inverter has just one filter inductor, which can decrease the system volume and improve the integration. In addition, the passive lossless snubber circuit achieves soft-switching by its own resonance, and all of the energy stored in the passive lossless snubber circuit can be transferred to load. A comparison between eight topologies is performed in this paper, and the analysis shows that the proposed soft-switching inverter topology has high reliability and efficiency. Finally, experimental results obtained with a 1 kW prototype verify the theoretical analysis and demonstrate the prominent characteristics of a reduced switching loss and improved efficiency.

High-Reliability Three-Phase Dual-Buck Grid-Connected Inverter without Shoot-Through Problem

  • Fu, Zhenbin;Feng, Zhihua;Chen, Xi;Zheng, Xinxin
    • Journal of Power Electronics
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    • v.19 no.2
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    • pp.454-462
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    • 2019
  • When compared to traditional bridge-type inverters, the dual-buck inverter has a higher reliability due to the fact that its bridge legs do not have a shoot-through problem. In this paper, the working principle of the dual-buck inverter is analyzed. A comparison of the working modes under full-cycle and half-cycle control is discussed. With half-cycle control, the inverter can realize a higher efficiency. However, this results in current zero-crossing distortion. The corresponding control strategy of the dual-buck inverter is proposed in order to realize both high efficiency and low current harmonic distortion. In addition, the system stability is analyzed. Dead-time is unnecessary due to the advantages of the topology. Thus, the current harmonic distortion can be further reduced. An inverter with the proposed control strategy has the advantages of high reliability, high efficiency and low current harmonic distortion. Finally, simulation and experimental results are given to verify the theoretical analysis.

Suppression of Zero Sequence Current Caused by Dead-time for Dual Inverter With Single Source (단전원 듀얼 인버터의 데드타임으로 인한 영상전류 억제 방법)

  • Yoon, Bum-Ryeol;Kim, Tae-Hyeong;Lee, June-Hee;Lee, June-Seok
    • The Transactions of the Korean Institute of Power Electronics
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    • v.27 no.2
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    • pp.126-133
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    • 2022
  • This study proposes a suppression of zero sequence current (ZSC), which is caused by zero sequence voltage (ZSV) for a dual two-level inverter with single DC bus. Large output voltages enable the dual inverter with single DC bus to improve a system efficiency compared with single inverter. However, the structure of dual inverter with single DC bus inevitably generates ZSC, which reduces the system efficiency and causes a current ripple. ZSV is also produced by dead time, and its magnitude is determined by the DC bus and current direction. This study presents a novel space vector modulation method that allows the instantaneous suppression of ZSC. Based on a condition where a switching period is twice a sampling (control) period, the proposed control method is implemented by injecting the offset voltage at the primary inverter. This offset voltage is injected in half of the switching period to suppress the ZSC. Simulation and experiments are used to compare the proposed and conventional methods to determine the ZSC suppression performance.

DUAL DUTY CYCLE CONTROLLED SOFT-SWITCHING HIGH FREQUENCY INVERTER USING AUXILIARY REVERSE BLOCKING SWITCHED RESONANT CAPACITOR

  • Bishwajit, Saha;Suh, Ki-Young;Lee, Hyun-Woo;Mutsuo, Nakaoka
    • Proceedings of the KIEE Conference
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    • 2006.10d
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    • pp.129-131
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    • 2006
  • This paper presents a new ZVS-PWM high frequency inverter. The ZVS operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. The operating principle and the operating characteristics of the new high frequency circuit treated here are illustrated and evaluated on the basis of simulation results. It was examined that the complete soft switching operation can be achieved even for low power setting ranges by introducing the high frequency dual duty cycle control scheme. In the proposed high frequency inverter treated here, the dual mode pulse modulation control strategy of the asymmetrical PWM in the higher power setting ranges and the lower power setting ones, the output power of this high frequency inverter could introduce in order to extend soft switching operation ranges. Dual duty cycle is used to provide a wide range of output power regulation that is important in many high frequency inverter applications. It is more suitable for induction heating applications the operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

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Half Load-Cycle Worked Dual Input Single Output DC/AC Inverter

  • Chen, Rong;Zhang, Jia-Sheng
    • Journal of Power Electronics
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    • v.14 no.6
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    • pp.1217-1223
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    • 2014
  • A novel half load-cycle worked dual input single output (DISO) DC/AC inverter is presented. The basic circuit consists of a dual buck regulator, which works in continuous current mode. The working principle of DISO DC/AC inverter has been used. The control method applied for half load-cycle worked DISO DC/AC inverter has been studied. The control effects of the open-loop proportional control and closed-loop proportional-integral control are compared by using PSIM software. The parameters are adopted in the realistic simulation and experiment test. Moreover, the waveforms, such as voltage of modulation reference signal and output voltage, were given. The simulation and experiment results proved that the half load-cycle worked DISO DC/AC inverter could achieve good performance, gain a line frequency of 50 Hz, and verify the correctness of theoretical analysis.