• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.583-585
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• 2012

In this paper, we introduce a design method for a broadband planar quasi-Yagi antenna (QYA) for terrestrial digital television (DTV) receiving. The coplanar strip line feeding the driver dipole is connected to a microstrip line and is terminated by short circuit. By appending a wide strip-type director at a location close to the driver dipole, a broadband impedance matching and a gain characteristics in a high frequency region are obtained. The gain characteristics in a low frequency region are improved by adding a reflector formed by a truncated ground plane. To reduce the antenna size, the strip-type dipole and reflector are modified to half bowtie (V)-shaped elements. The effects of various parameters on the antenna characteristics are examined. An antenna, as an design example for the proposed antenna, is designed for the operation in the frequency band of 470-806 MHz for terrestrial DTV. The optimized antenna is fabricated on an FR4 substrate and tested experimentally to verify the results of this study.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.143-153
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• 2014

This paper presents a novel application of LCC resonant converter for 60kW EV fast charger and describes development of the high efficiency 60kW EV fast charger. The proposed converter has the advantage of improving the system efficiency especially at the rated load condition because it can reduce the conduction loss by improving the resonance current shape as well as the switching loss by increasing lossless snubber capacitance. Additionally, the simple gate driver circuit suitable for proposed topology is designed. Distinctive features of the proposed converter were analyzed depending on the operation modes and detail design procedure of the 10kW EV fast charger converter module using proposed converter topology were described. The proposed converter and the gate driver were identified through PSpice simulation. The 60kW EV fast charger which generates output voltage ranges from 50V to 500V and maximum 150A of output currents using six parallel operated 10kW converter modules were designed and implemented. Using 60kW fast charger, the charging experiments for three types of high-capacity batteries were performed which have a different charging voltage and current. From the simulation and experimental results, it is verified that the proposed converter topology can be effectively used as main converter topology for EV fast charger.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.550-551
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• 2013

Large-area RF-driven ion source is being developed at Germany for the heating and current drive of ITER plasmas. Negative hydrogen (deuterium) ion sources are major components of neutral beam injection systems in future large-scale fusion experiments such as ITER and DEMO. RF ion sources for the production of positive hydrogen ions have been successfully developed at IPP (Max-Planck- Institute for Plasma Physics, Garching) for ASDEX-U and W7-AS neutral beam injection (NBI) systems. In recent, the first NBI system (NBI-1) has been developed successfully for the KSTAR. The first and second long-pulse ion sources (LPIS-1 and LPIS-2) of NBI-1 system consist of a magnetic bucket plasma generator with multi-pole cusp fields, filament heating structure, and a set of tetrode accelerators with circular apertures. There is a development plan of large-area RF ion source at KAERI to extract the positive ions, which can be used for the second NBI (NBI-2) system of KSTAR, and to extract the negative ions for future fusion devices such as ITER and K-DEMO. The large-area RF ion source consists of a driver region, including a helical antenna (6-turn copper tube with an outer diameter of 6 mm) and a discharge chamber (ceramic and/or quartz tubes with an inner diameter of 200 mm, a height of 150 mm, and a thickness of 8 mm), and an expansion region (magnetic bucket of prototype LPIS in the KAERI). RF power can be transferred up to 10 kW with a fixed frequency of 2 MHz through a matching circuit (auto- and manual-matching apparatus). Argon gas is commonly injected to the initial ignition of RF plasma discharge, and then hydrogen gas instead of argon gas is finally injected for the RF plasma sustainment. The uniformities of plasma density and electron temperature at the lowest area of expansion region (a distance of 300 mm from the driver region) are measured by using two electrostatic probes in the directions of short- and long-dimension of expansion region.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.249-256
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• 2007

AIn this paper, a new desist of LDI controller IC for general purpose is proposed for driving the LDI(LCD Driver Interface) controller in $4{\sim}9$ inches sized portable small-medium TFT-LCD(Thin Film Transistor addressed -Liquid Crystal Display) panel module. The designed LDI controller was verified on the FPGA(Reld Programmable Gate Array) test board, and was made the interactive operation with the commercial TFT-LCD panel successfully. The purpose of design is that it is standardized the LDI controller's operation by one LDI controller for driving all TFT-LCD panel without classifying the panel vendor, and size. The main advantage for new general-purpose LDI controller is the usage for the desist of all panel's SoG(System on a Glass) module because of the design for the standard operation. And in the previous method, it used each LDI controller for every LCD vendor, and panel size, but because a new one can drive all portable small-medium sized panel, it results in reduction of LDI controller supply price, and manufacturing cost of AV(Audio Video) board and panel. In the near future, the development of SoG IC(Integrated Circuit) for manufacturing more excellent functional TFT-LCD panel module is necessary. As a result of this research, the TFT-LCD panel can make more small size, and light weight, and it results in an upturn of domestic company's share in the world market. With the suggested theory in this paper, it expects to be made use of a basic data for developing and manufacturing for the SoG chip of TFT-LCD panel module.

• Journal of the Korean Society of Marine Environment & Safety
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• v.21 no.1
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• pp.97-102
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• 2015

The long line fishing machine is combined with motor and two disc rollers has used on the small size fishing-boat under 1 ton located in near Jeollanam-do seaside. The long line fishing motor is controlled only one direction because the fishing line is loaded heavily at pulling up. On this paper we made the long line fishing 400W power motor controller which it was usually applied under 1 ton fishing boat, and designed the controller using PWM chip, Half bridge driver and MOSFET for one direction motor control. Furthermore some user convenience devices were added like battery indicator and safety protection circuit for battery overdischarge and battery source wire mismatch connection. So we protected the battery from overdicharging when the battery voltage was below 11.5V and fishermen didn't need to worry about source lines misconnection anymore. We confirmed the test version of controller was the good working condition at land and sea.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4165-4170
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• 2012

In this paper, a method for the improvement in the gain and bandwidth of a microstrip-fed broadband planar quasi-Yagi antenna (QYA) is studied. The broadband characteristics of the QYA are achieved from the coplanar strip-fed planar dipole driver and a parasitic director close to the driver. In order to obtain stable gain variation over the required frequency band, a director and a ground reflector are appended to the driver having a nearby parasitic director. The QYA is fed through an integrated balun composed of a microstrip line and a slot line which are terminated in a short circuit. By adjusting the feeding point, a broadband impedance matching is obtained. A QYA with an operating frequency band of 1.75-2.7 GHz and a gain > 4.5 dBi is designed and fabricated on an FR4 substrate with dielectric constant of 4.4 and thickness of 1.6mm. The experimental results show that the fabricated antenna has good performance such as a broad bandwidth of 59.7%(1.55-2.87 GHz), a stable gain between 4.7-6.5 dBi, and a front-to-back ratio > 10 dB. The measured data agree well with the simulation, which validates this study.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.3
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• pp.491-499
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• 2019

Recently, there has been increasing demand for power quality in power supply devices. The IEC 61000-3-2 standard requires that the AC / DC power supply for lighting meet the specifications for the power factor (PF) and total waveform distortion (THD). In addition, advanced countries in Europe are regulating the ripple rate as 15 ~ 30% for the flicker phenomenon caused by the change in the amount of foot energy due to the change in current of the output terminal. Therefore, domestic standards and regulations are being updated. This study adopted the Flyback converter to satisfy the PFC standard, and has the circuit first and second insulation function. To reduce the low frequency ripple of the LED current, Flyback, Coupled Inductor, LC parallel resonance filter, LLC resonance filter, and Cuk were simulated by PSIM to mimic each LED driving circuit. A coupled LC resonant circuit with a coupled inductor on the primary side and LC resonance on the secondary side was also proposed for output side ripple reduction.