• Title/Summary/Keyword: driver circuit

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Integrated Gate Driver Circuit Using a-Si TFT with AC-Driven Dual Pull-down Structure

  • Jang, Yong-Ho;Yoon, Soo-Young;Kim, Binn;Chun, Min-Doo;Cho, Hyung-Nyuck;Cho, Nam-Wook;Sohn, Choong-Yong;Jo, Sung-Hak;Choi, Seung-Chan;Kim, Chang-Dong;Chung, In-Jae
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.944-947
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    • 2005
  • Highly stable gate driver circuit using a-Si TFT has been developed. The circuit has dual-pull down structure, in which bias stress to the TFTs is relieved by alternating applied voltage. The circuit has been successfully integrated in 4-in. QVGA and 14-in. XGA TFT-LCD with a normal a-Si process, which are stable for over 2,000 hours at $60^{\circ}C$. The enhancement of stability of the circuit is attributed to retarded degradation of pull-down TFTs by AC driving.

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An Optimized Stacked Driver for Synchronous Buck Converter

  • Lee, Dong-Keon;Lee, Sung-Chul;Jeong, Hang-Geun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.186-192
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    • 2012
  • Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

An Equaivalent Circuit Model for Rquantum Well Laser Diodes (양자우물 레이저 다이오드의 등가회로 모델)

  • 이승우;김대욱;최우영
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.1
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    • pp.49-58
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    • 1998
  • In this paper, a new equivalent circuit model for quantum-well laser diode (LD) is proposed. The model includes carrier transport effects in the SCH region, and rprovides, in a stable and accurate manner, large-and small-signal responses of laser diode output power as function of injected currents. SPICE simulation was performed using the circuit model and results are presented for L-I characteristics, pulse and frequency responses under various conditions. It is expencted that the new equaivalent circuit model will find useful applications for designing and analyzing OEIC, LD driver circuits, and LD packaging.

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A MOSFET Pushpull Circuit which Prevents the Output Circuit from Oscillation Causing Reverse Recovery Current of MOSFET and Parastic Components (역회복전류와 기생소자들에 의한 발진 방지용 MOSFET 푸쉬풀 회로)

  • Jeong, Jae-Hoon;Cho, Gyu-Hyeong;Ahn, Che-Hong
    • Proceedings of the KIEE Conference
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    • 1996.07b
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    • pp.1292-1294
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    • 1996
  • The general output circuit for PWM output is pushpull using a complimentary MOSFET. The gate driver coupled directly at gate can switch easy upto a high frequency. However, a high reverse recovery current and parastic components make a oscillation output. This paper analyses this phenomenon and proposes a novel output circuit preventing the oscillation.

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A Ringing Surge Clamper Type Active Auxiliary Edge-Resonant DC Link Snubber-Assisted Three-Phase Soft-Switching Inverter using IGBT-IPM for AC Servo Driver

  • Yoshitsugu, Junji;Yoshida, Masanobu;Hiraki, Eiji;Inoue, Kenji;Ahmed, Tarek;Nakaoka, Mutsuo
    • KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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    • v.2B no.3
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    • pp.115-124
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    • 2002
  • This paper presents an active auxiliary edge-resonant DC link snubber with a ringing surge damper and a three-phase voltage source type zero voltage soft-switching inverter with the resonat snubber treated here for the AC servo motor driver applications. The operation of the active auxiliary edge-resonant DC link snubber circuit with PWM voltage is described, together with the practical design method to select its circuit parameters. The three-phase voltage source type soft-switching inverter with a single edge-resonant DC link snubber treated here is evaluated and discussed for the small-scale permanent magnet (PM) type-AC servo motor driver from an experimental point of view. In addition to these, the AC motor stator current and its motor speed response for the proposed three-phase soft-switching inverter employing Intelligent Power Module(IPM) based on IGBTS are compared with those of the conventional three-phase hard-switching inverter using IPM. The practical effectiveness of the three-phase soft-switching inverter-fed permanent magnet type AC motor speed tracking servo driver is proven on the basis of the common mode current in a novel type three-phase soft-switching inverter-fed AC motor side and the conductive noise on the mains terminal interface voltage as compared with those of the conventional three-phase hard-switching inverter-fed permanent magnet type AC servo motor driver for the speed tracking applications.

Design of Power IC Driver for AMOLED (AMOLED 용 Power IC Driver 설계)

  • Ra, Yoo-Chan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.19 no.5
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    • pp.587-592
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    • 2018
  • Because the brightness of an AMOLED is determined by the flowing current, each pixel of AMOLED operates via A current driving method. Therefore, it is necessary to supply power to adjust the amount of current according to THE user's requirement for AMOLED driving. In this study, an IP driver block was designed and a simulation was conducted for an AMOLED display, which supplies power as selected by users. The IP driver design focused on regulating the output power due to the OLED characteristics for the diode electric current according to the voltage to be activated by pulse-skipping mode (PSM) under low loads, and 1.5 MHz pulse-width modulation (PWM) for medium/high loads. The IP driver was designed to eliminate the ringing effects appearing from the dis-continue mode (DCM) of the step-up converter. The ringing effects destroy the power switch within the IC, or increase the EMI to the surrounding elements. The IP driver design minimized this through a ringing killer circuit. Mobile applications were considered to enable true shut-down capability by designing the standby current to fall below $1{\mu}A$ to disable it. The driver proposed in this paper can be applied effectively to the same system as the AMOLED display dual power management circuit.

Implementation of Visible Light Communication System Modulated by a Switching Driver Circuit of Lighting LED (조명용 LED의 스위칭 구동 회로로 변조되는 가시광 통신 시스템의 구현)

  • Cho, Sang-Ho;Han, Sang-Kyoo;Roh, Chung-Wook;Hong, Sung-Soo;Jang, Byung-Jun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.8
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    • pp.905-910
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    • 2010
  • In this paper, visible light communication(VLC) system modulated by a switching driver circuit of lighting light emitting diode(LED), not only for illumination but also for optical wireless communication, is implemented. Presented system could overcome the drawbacks of prior linear modulation technique such as low efficiency, heat generation, and limits to realization of high power lighting LED. Experimental results from the realized digital audio system are presented to confirm the superiority of the proposed circuit. Our prototype achieves a transmission data rate of 10 Mbps with a radius of 1.5 meters using 20 W output power, and the signals were detected successfully.

A Power MOSFET Driver with Protection Circuits (보호 회로를 포함한 전력 MOSFET 구동기)

  • Han, Sang-Chan;Lee, Soon-Seop;Kim, Soo-Won;Lee, Duk-Min;Kim, Seong-Dong
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.2
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    • pp.71-80
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    • 1999
  • In this paper, a power MOSFET driver with protection circuits is designed using a 2${\mu}m$ high-voltage CMOS process. For stable operations of control circuits a power managing circuit is designed, and a voltage-detecting short-circuit protection(VDSCP) is proposed to protect a voltage regulator in the power control circuit. The proposed VDSCP scheme eliminates voltage drop caused by a series resistor, and turns off output current under short-circuit state. To protect a power MOSFET, a short-load protection, a gate-voltage limiter, and an over-voltage protection circuit are also designed A high voltage 2 ${\mu}m$ technology provides the breakdown voltage of 50 V. The driver consumes the power of 20 ~ 100 mW along its operation state excluding the power of the power MOSFET. The active area of the power MOSFET driver occupies $3.5 {\times}2..8mm^2$.

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Design of the Noise Margin Improved High Voltage Gate Driver IC for 300W Resonant Half-Bridge Converter (잡음 내성이 향상된 300W 공진형 하프-브리지 컨버터용 고전압 구동 IC 설계)

  • Song, Ki-Nam;Park, Hyun-Il;Lee, Yong-An;Kim, Hyoung-Woo;Kim, Ki-Hyun;Seo, Kil-Soo;Han, Seok-Bung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.7-14
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    • 2008
  • In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

Design of Core Chip for 3.1Gb/s VCSEL Driver in 0.18㎛ CMOS (0.18㎛ CMOS 3.1Gb/s VCSEL Driver 코아 칩 설계)

  • Yang, Choong-Reol;Lee, Sang-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.1
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    • pp.88-95
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    • 2013
  • We propose a novel driver circuit design using $0.18{\mu}m$ CMOS process technology that drives a 1550 nm high-speed VCSEL used in optical transceiver. We report a distinct improvement in bandwidth, voltage gain and eye diagram at 3.1Gb/s data rate in comparison with existing topology. In this paper, the design and layout of a 3.1Gb/s VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed.