• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.1-9
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• 2000

A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1579-1587
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• 1999

Bias-dependent noise models of $0.2\mu\textrm{m}$ gate length P-HEMT's which are scalable with gate width are proposed. To predict S-parameters of the P-HEMT's the intrinsic parameters except for $\tau$ subtracted the offsets introduced in this paper are normalized to the gate width and then scaled. The small-signal model parameters are expressed as fitting functions of the drain current to $\textrm{I}_{dss}$ ratio and gate width. In addition, to estimate accurately noise parameters the noise temperature $\textrm{T}_{g}$ of the intrinsic resistance, the equivalent noise conductance $\textrm{G}_{ni}$ of the gate current noise source, and the equivalent noise conductance $\textrm{G}_{no}$ of the drain current noise source are adopted as the noise model parameters. The extracted values of $\textrm{T}_{g}$ are nearly independent of drain current and gate width and their average is around the ambient temperature. The extracted values of $\textrm{G}_{ni}$ are small enough to be neglected to the circuit characteristics. From the comparison of the noise model with only $\textrm{G}_{no}$ and that having $\textrm{T}_{g}$, $\textrm{G}_{ni}$ and $\textrm{G}_{no}$ to the measured data it is fund that even the former model is in good agreement with the measured noise parameters. Thus, from a practical point of view the noise model having only the drain current noise source is confirmed as a scalable bias-dependent model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.3
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• Journal of the Korean Geosynthetics Society
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• v.7 no.4
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• pp.37-45
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• 2008

A pilot test using environmentally friendly drains, was carried out to evaluate their applicability potential in the field. The pilot test site was divided into 5 different areas, with several combinations of vertical and horizontal drains installed for evaluation. Conventional natural fiber drains (FDB), new developed straw drain board (SDB) and plastic drain board (PDB) were used as vertical drains, while sand and fiber mats were used as horizontal drains. Surface settlement rates and excess pore pressure generation/dissipation tendency of PDB and FDB are almost identical except those of SDB. Cone tip resistance obtained from cone penetration test measured at the end of 1st consolidation stage for upper soft layer definitely increased irrespective of types of vertical drains. The monitoring and site investigation test data obtained at the pilot test site prove the vertical natural fiber drains can be used as substitutes of conventional plastic and sand material.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.25-32
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• 2005

In this paper, it is attempted to provide a unified explanation for typical short channel GaAs MESFET’s and SOI-structured Si JFET's behaviors such as: i) drain voltage-induced threshold voltage roll-off, ii) finite output ac resistance beyond the saturation, and iii) weak dependence of the drain saturation current on the channel length. Replacing the conventional GCA with a new assumption that is suggested in order to include the longitudinal field variation, and taking into account the channel current continuity and the field-dependent mobility, we can derive the two-dimensional potential in both depletion region and undepleted conducting channel. Obtained expressions for the threshold voltage and the drain current will be considerably accurate over the entire operating region. Moreover, in comparison with the conventional channel length shortening models, our model seems to be more reasonable in explaining the Early effect.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.123-129
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• 1996

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.9
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• pp.835-843
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• 2008

We have fabricated the source-drain electrodes for OTFTs by screen printing method and manufactured Ag pastes as conductive paste. To obtain excellent conductivity and screen-printability of Ag pastes, the dispersion characteristics of Ag pastes prepared from two types of acryl resins with different molecular structures and Ag powder treated with caprylic acid, triethanol amine and dodecane thiol as surfactant respectively were investigated. The Ag pastes containing Ag powder treated with dodecane thiol having thiol as anchor group or AA4123 with carboxyl group(COOH) of hydrophilic group as binder resin exhibited excellent dispersity. But, Ag pastes(CA-41, TA-41, DT-41) prepared from AA4123 fabricated the insulating layer since the strong interaction between surface of Ag powder and carboxyl group(COOH) of AA4123 interfered with the formation of conduction path among Ag powders. The viscosity behavior of Ag pastes exhibited shear-thinning flow in the high shear rate range and the pastes with bad dispersion characteristic demonstrated higher shear-thinning index than those with good dispersity due to the weak flocculated network structure. The output curve of OTFT device with a channel length of 107 ${\mu}m$ using screen-printed S-D electrodes from DT-30 showed good saturation behavior and no significant contact resistance. And this device exhibited a saturation mobility of $4.0{\times}10^{-3}$ $cm^2/Vs$, on/off current ratio of about $10^5$ and a threshold voltage of about 0.7 V.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Geomechanics and Engineering
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• v.7 no.5
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• pp.525-537
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• 2014

The typical design of ground improvement with prefabricated vertical drains (PVD) and surcharge preloading involves a series of deterministic analyses using averaged or mean soil properties for the various combination of the PVD spacing and surcharge preloading height that would meet the criteria for minimum consolidation time and required degree of consolidation. The optimum design combination is then selected in which the total cost of ground improvement is a minimum. Considering the variability and uncertainties of the soil consolidation parameters, as well as considering the effects of soil disturbance (smear zone) and drain resistance in the analysis, this study presents a stochastic cost optimization of ground improvement with PVD and surcharge preloading. Direct Monte Carlo (MC) simulation and importance sampling (IS) technique is used in the stochastic analysis by limiting the sampled random soil parameters within the range from a minimum to maximum value while considering their statistical distribution. The method has been verified in a case study of PVD improved ground with preloading, in which average results of the stochastic analysis showed a good agreement with field monitoring data.