• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.345-345
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• 2010

1T-DRAM cell with solid phase (SPC) crystallized poly-Si thin film transistor was fabricated and electrical characteristics were evaluated. The fabricated device showed kink effect by negative back bias. Kink current is due to the floating body effect and it can be used to memory operation. Current difference between "1" state and "0" state was defined and the memory properties can be improved by using gate induced drain leakage (GIDL) current.

• ETRI Journal
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• 제34권4호
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• pp.633-636
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• 2012

A dynamic analysis of an amorphous silicon (a-Si) thin film transistor liquid crystal display (TFT-LCD) pixel is presented using new a-Si TFT and liquid crystal (LC) capacitance models for a Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. This dynamic analysis will be useful when predicting the performance of LCDs. The a-Si TFT model is developed to accurately estimate a-Si TFT characteristics of a bias-dependent gate to source and gate to drain capacitance. Moreover, the LC capacitance model is developed using a simplified diode circuit model. It is possible to accurately predict TFT-LCD characteristics such as flicker phenomena when implementing the proposed simulation model.

• 한국전자파학회논문지
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• 제7권2호
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• pp.178-185
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• 1996

In this paper, a theoretical analysis of a wide band distributed mixer using a dual-gate GaAs MESFET's(DGFET) is introduced. Based on low noise mixer mode(LNM) region modeling of DGFET, variation of g/sub m/ and conversion gain are presented versus bias. The distributed mixer is composed of drain and gate transmission line, m-derived image impedance matching circuits at each input and output port, and DGFET's. Through computer simulation, wide-band characteristics of designed distributed mixer are confirmed. And, it is certificated that LO/RF isolation between gate 1 and gate 2 is obtained more than 15dB.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 춘계종합학술대회
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• pp.321-324
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• 2001

MOSFET는 전력감소, 도핑농도 증가, 캐리어 속도 증가를 위해서 많은 변화를 가져왔다. 이러한 변화를 받아들이기 위해서, 채널의 길이와 공급전압이 감소해야만했으며, 그것으로 인해 소자가 더욱 작아지게 되었다. 본 논문에서는 이러한 변화를 두 가지의 시뮬레이터를 사용하여 비교 분석하였다. 사용되어진 시뮬레이터는 Micro-Tec과 ISE-TCAD이며, 본 논문에서 LDD(lightly-doped drain) MOSFET에 관하여 시뮬레이션 하였다. 게이트 길이는 180nm를 기준으로 MOSFET의 특성과 전계를 비교 분석하였다.

• E2M - 전기 전자와 첨단 소재
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• 제10권8호
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• pp.783-793
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• 1997

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density stress current transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width $\times$ length 10 $\times$1${\mu}{\textrm}{m}$, 10 $\times$ 0.3${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• 전자공학회논문지A
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• 제28A권9호
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• pp.736-742
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• 1991

N$^{+}$poly gate NMOSFETs and p$^{+}$ poly gate (surface type) PMOSFETs with three different gate oxides(SiO2, NO, and ONO) were fabricated. The rapid thermal nitridation and reoxidation techniques have been applied to gate oxide formation. The current drivability of the ONO NMOSFET shows larger values than that of the SiO2 NMOSFET. The snap-back occurs at a lower drain voltage for SiO$_2$ cases for ONO NMOSFET. Under the maximum substrate current bias conditions, hot-carrier effects inducting threshold voltage shift and transconductance degradation were investigated. The results indicate that ONO films exhibit less degradation in terms of threshold voltage shift. It was confirmed that the ONO samples achieve good improvement of hot-carrier immunity. In a SiO$_2$ SC-PMOSFET, with significant boron penetration, it becomes a depletion type (normally-on). But ONO films show excellent impurity barrier properties to boron penetration from the gate.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.73-76
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• 2020

The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantum-mechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.69.3-69.3
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• 2012

A high-performance low-voltage graphene field-effect transistor (FED array was fabricated on a flexible polymer substrate using solution-processable, high-capacitance ion gel gate dielectrics. The high capacitance of the ion gel, which originated from the formation of an electric double layer under the application of a gate voltage, yielded a high on-current and low voltage operation below 3 V. The graphene FETs fabricated on the plastic substrates showed a hole and electron mobility of 203 and 91 $cm^2/Vs$, respectively, at a drain bias of - I V. Moreover, ion gel gated graphene FETs on the plastic substrates exhibited remarkably good mechanical flexibility. This method represents a significant step in the application of graphene to flexible and stretchable electronics.

• 대한전자공학회논문지
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• 제24권5호
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• pp.818-822
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• 1987

Gate capacitances have been measured directly on small-geometry MOSFET's with the drain voltage as a parameter for various channel lengths and for p and n channel types and the characteristics have been compared with each other. The influence of 'hot carrier effect' of short channel devices on capaciatance has been compared with long channel devices. The results show that gate capacitance characteristics of short channel device deviate from those of long channel device. The accuracy of the measurement system is less than a few femto Farad, and the minimum geometry (W/L) of device for which reliable measurement can be obtained is 6/3.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.445-448
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• 1999

In this Paper, we present simple physical model of the Capacitance characteristics for GaAs MESFET\`s in wide temperatures. In this model, gate-source and gate-drain capacitances are represented by analytical expressions which are classified into three different regions for bias voltage. This model contained the temperature dependent variable that is the built-in voltage and the depletion width. Using the equations obtained in this work a submicron gate length MESFET has simulated and theoretical result are in good agreement with the experimental measurement.