• Journal of IKEEE
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• v.26 no.4
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• pp.553-559
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• 2022

In this paper, RC snubber circuit design technology for oscillation suppression in half-bridge configuration of cascode gallium nitride (GaN) field effect transistors (FETs) is analyzed. A typical wide band-gap (WBG) device, cascode GaN FET, has excellent high-speed switching characteristics. However, due to such high-speed switching characteristics, a false turn-off problem is caused, and an RC snubber circuit is essential to suppress this. In this paper, the commonly used experimental-based RC snubber design technique and the RC snubber design technique using the root locus method are compared and analyzed. In the general method, continuous circuit changes are required until the oscillation suppression performance requirement is met based on experimental experience . However, in root locus method, the initial value can be set based on the non-oscillation R-C map. To compare the performance of the two aforementioned design methods, a simulation experiment and a switching experiment using an actual double pulse circuit are performed.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.39-45
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• 1997

This study presents the first experimental data for the impact of hot-carrier degradtion on the performance of CMOS folded-cascode op-amps. A folded-cascode op-amp which has an NMOS input pair has been designed and fabricated using a 0.8.mu.m single-poly, double-metal CMOS process. After high voltage stress, the degradtion of perfomrance parameters such as open-metal CMOS process. After high voltage stress, the degradation of performance parameters such as open-loop voltage gain, unity-gain frequency and phase margin has been analized and physically explaniend in terms of hot carrier degradation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of electromagnetic engineering and science
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• v.3 no.1
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• pp.1-6
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• 2003

In this paper, a sub-harmonic dual-gate FET mixer is suggested to improve the isolation characteristic between LO and RF ports of an unbalanced mixer. The mixer was designed by using single-gate FET cascode structure and driven by the second harmonic component of LO signal. A dual-gate FET mixer has good isolation characteristic since RF and LO signals are injected into gatel and gate2, respectively. In addition, the isolation characteristic of a sub-harmonic mixer is better than that of a fundamental mixer due to the large frequency separation between the LO and RF frequencies. As RF power was -30 ㏈m and LO power was 0 ㏈m, the designed mixer yielded the -47.17 ㏈m LO-to-RF leakage power level, 10 ㏈ conversion gain, -2.5 ㏈m OIP3, -12.5 ㏈m IIP3 and -1 ㏈m 1 ㏈ gain compression point. Since the LO-to-RF leakage power level of the designed mixer is as good as that of a double-balanced mixer, the sub-harmonic dual-gate FET mixer can be utilized instead.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.168-172
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• 2003

This paper analyzes the output noise and the noise figure of common source MOSFET pair each input of which is separately driven in the different frequencies. This analysis is performed for concurrent dual band cascode CMOS LNA with double inputs and single output fabricated in $0.18{\mu}m$ CMOS process. Since both inputs and output are matched to near $50{\Omega}$ using on-chip inductors, the measured noise figures are much higher than those of usual CMOS LNA. But, the main concern of this paper is focused on the added noise features due to the other channel common source stage. The dual-band LNA results in noise figure of 4.54dB at 2.14GHz and 6.03dB at 5.25GHz for selectable operation and 7.44dB and 6.58dB for concurrent operation. The noise analysis explains why the added noise at each band shows so large difference.

• Journal of Sensor Science and Technology
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• v.16 no.6
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• pp.475-483
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• 2007

This paper proposes a readout integrated circuit (ROIC) for $32{\times}32$ infrared focal plane array (IRFPA) detector, which consist of reference resistor, detector resistor, reset switch, integrated capacitor and operational amplifier. Proposed ROIC is designed using $0.35{\;}{\mu}m$ 2P-4M (double poly four metal) n-well CMOS process parameters. Low noise folded cascode operational amplifier which is a key element in the ROIC showed 12.8 MHz unity-gain bandwidth and open-gain 89 dB, phase margin $67^{\circ}$, SNR 82 dB. From proposed circuit, we gained output voltage variation ${\Delta}17{\};mV/^{\circ}C$ when the detector resistor varied according to the temperature.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.