• Title/Summary/Keyword: double gate MOSFET

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Analysis of Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Concentration (비대칭 DGMOSFET의 채널도핑농도에 따른 드레인 유도 장벽 감소현상 분석)

  • Jung, Hakkee;Kwon, Ohshin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.858-860
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    • 2015
  • 본 연구에서는 비대칭 이중게이트 MOSFET의 채널 내 도핑농도에 대한 드레인 유도 장벽 감소 현상에 대하여 분석하고자한다. 드레인 유도 장벽 감소 현상은 드레인 전압에 의하여 소스 측 전위장벽이 낮아지는 효과로서 중요한 단채널 효과이다. 이를 분석하기 위하여 포아송방정식을 이용하여 해석학적 전위분포를 구하였으며 전위분포에 영향을 미치는 채널도핑 농도뿐만이 아니라 상하단 산화막 두께, 하단 게이트 전압 등에 대하여 드레인 유도 장벽 감소 현상을 관찰하였다. 결과적으로 드레인 유도 장벽 감소 현상은 채널도핑 농도에 따라 큰 변화를 나타냈다. 단채널 효과 때문에 채널길이가 짧아지면 도핑농도에 따른 영향이 증가하였다. 도핑농도에 대한 드레인유도장벽감소 현상의 변화는 상하단 산화막 두께에 따라 큰 변화를 보였으며 산화막 두께가 증가할수록 도핑농도에 따른 변화가 증가하는 것을 알 수 있었다. 또한 하단게이트 전압은 그 크기에 따라 도핑농도의 영향이 변화하고 있다는 것을 알 수 있었다.

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Analysis of Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Profile (비대칭 DGMOSFET의 채널도핑분포함수에 따른 드레인 유도 장벽 감소현상 분석)

  • Jung, Hakkee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.863-865
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    • 2015
  • 본 연구에서는 비대칭 이중게이트 MOSFET의 채널 내 도핑농도분포에 대한 드레인유도장벽감소(Drain Induced Barrier Lowering; DIBL)에 대하여 분석하고자한다. DIBL은 드레인 전압에 의하여 소스 측 전위장벽이 낮아지는 효과로서 중요한 단채널 효과이다. 이를 분석하기 위하여 포아송방정식을 이용하여 해석학적 전위분포를 구하였으며 전위분포에 영향을 미치는 채널도핑농도의 분포함수변화에 대하여 DIBL을 관찰하였다. 채널길이, 채널두께, 상하단 게이트 산화막 두께, 하단 게이트 전압 등을 파라미터로 하여 DIBL을 관찰하였다. 결과적으로 DIBL은 채널도핑농도분포함수의 변수인 이온주입범위 및 분포편차에 변화를 나타냈다. 특히 두 변수에 대한 DIBL의 변화는 최대채널도핑농도가 $10^{18}/cm^3$ 정도로 고도핑 되었을 경우 더욱 현저히 나타나고 있었다. 채널길이가 감소할수록 그리고 채널두께가 증가할수록 DIBL은 증가하였으며 하단 게이트 전압과 상하단 게이트 산화막 두께가 증가할수록 DIBL은 증가하였다.

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Analysis of Threshold Voltage Characteristics for Double Gate MOSFET Based on Scaling Theory (스켈링이론에 따른 DGMOSFET의 문턱전압 특성분석)

  • Jung, Hak-Kee;Han, Ji-Hyung;Jeong, Dong-Soo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.683-685
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    • 2012
  • This paper have presented the analysis of the change for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET with two gates to be next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold chatacteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering is changed, and the deviation rate is changed for device parameters for DGMOSFET.

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Subthreshold Characteristics of Double Gate MOSFET for Gaussian Function Distribution (가우스함수의 형태에 따른 DGMOSFET의 문턱전압이하특성)

  • Jung, Hak-Kee;Han, Ji-Hyung;Lee, Jong-In;Kwon, Oh-Shin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.716-718
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    • 2012
  • This paper have presented the change for subthreshold characteristics for double gate(DG) MOSFET based on scaling theory and the shape of Gaussian function. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution and consequently potential distributions have been analyzed closely for experimental results, and the subthreshold characteristics have been analyzed for the shape parameters of Gaussian function such as projected range and standard projected deviation. Since this potential model has been verified in the previous papers, we have used this model to analyze the subthreshold chatacteristics. The scaling theory is to sustain constant outputs for the change of device parameters. As a result to apply the scaling theory for DGMOSFET, we know the subthreshold characteristics have been greatly changed, and the change of threshold voltage is bigger relatively.

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Subthreshold Characteristics of Double Gate MOSFET for Gaussian Function Distribution (도핑분포함수의 형태에 따른 DGMOSFET의 문턱전압이하특성)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.6
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    • pp.1260-1265
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    • 2012
  • This paper have presented the change for subthreshold characteristics for double gate(DG) MOSFET based on scaling theory and the shape of Gaussian function. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution and consequently potential distributions have been analyzed closely for experimental results, and the subthreshold characteristics have been analyzed for the shape parameters of Gaussian function such as projected range and standard projected deviation. Since this potential model has been verified in the previous papers, we have used this model to analyze the subthreshold chatacteristics. The scaling theory is to sustain constant outputs for the change of device parameters. As a result to apply the scaling theory for DGMOSFET, we know the subthreshold characteristics have been greatly changed, and the change of threshold voltage is bigger relatively.

Analysis of Threshold Voltage and DIBL Characteristics for Double Gate MOSFET Based on Scaling Theory (스켈링 이론에 따른 DGMOSFET의 문턱전압 및 DIBL 특성 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.1
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    • pp.145-150
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    • 2013
  • This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

Analysis of Channel Doping Profile Dependent Threshold Voltage Characteristics for Double Gate MOSFET (이중게이트 MOSFET의 채널도핑분포의 형태에 따른 문턱전압특성분석)

  • Jung, Hak-Kee;Han, Ji-Hyung;Lee, Jae-Hyung;Jeong, Dong-Soo;Lee, Jong-In;Kwon, Oh-Shin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.05a
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    • pp.664-667
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    • 2011
  • In this paper, threshold voltage characteristics have been analyzed as one of short channel effects occurred in double gate(DG)MOSFET to be next-generation devices. The Gaussian function to be nearly experimental distribution has been used as carrier distribution to solve Poisson's equation, and threshold voltage has been investigated according to projected range and standard projected deviation, variables of Gaussian function. The analytical potential distribution model has been derived from Poisson's equation, and threshold voltage has been obtained from this model. Since threshold voltage has been defined as gate voltage when surface potential is twice of Fermi potential, threshold voltage has been derived from analytical model of surface potential. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the threshold voltage characteristics have been considered according to the doping profile of DGMOSFET.

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Analysis on DIBL of DGMOSFET for Device Parameters

  • Jung, Hak-Kee
    • Journal of information and communication convergence engineering
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    • v.9 no.6
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    • pp.738-742
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    • 2011
  • This paper has studied drain induced barrier lowering(DIBL) for Double Gate MOSFET(DGMOSFET) using analytical potential model. Two dimensional analytical potential model has been presented for symmetrical DGMOSFETs with process parameters. DIBL is very important short channel effects(SCEs) for nano structures since drain voltage has influenced on source potential distribution due to reduction of channel length. DIBL has to be small with decrease of channel length, but it increases with decrease of channel length due to SCEs. This potential model is used to obtain the change of DIBL for DGMOSFET correlated to channel doping profiles. Also device parameters including channel length, channel thickness, gate oxide thickness and doping intensity have been used to analyze DIBL.

$H_2$ sensor for detecting hydrogen in DI water using Pd membrane (수중 수소 감지를 위한 MISFET형 센서제작과 그 특성)

  • Cho, Yong-Soo;Son, Seung-Hyun;Choi, Sie-Young
    • Journal of Sensor Science and Technology
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    • v.9 no.2
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    • pp.113-119
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    • 2000
  • In this work, Pd/Pt gate MISFET sensor using Pd membrane was fabricated to detect the hydrogen in DI water. A differential pair-type was used to minimize the intrinsic voltage drift of the MISFET. To avoid hydrogen induced drift of the sensor, the silicon dioxide/silicon nitride double layer was used as the gate insulator of the FET's. In order to eliminate the blister formation on the surface of the hydrogen sensing gate metal, Pd/Pt double metal layer was deposited on the gate insulator. For this type of application sensors need to be isolated from the DI water, and a Pd membrane was used to separate the sensor from the DI water. The output voltage change due to the variation of hydrogen concentration is linear from 100ppm to 500 ppm.

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A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

  • Son, Won-So;Kim, Sang-Gi;Sohn, Young-Ho;Choi, Sie-Young
    • ETRI Journal
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    • v.26 no.1
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    • pp.7-13
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    • 2004
  • To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

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