• Journal of Power Electronics
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• v.16 no.3
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• pp.915-924
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• 2016

A digital self-sustained phase shift modulation (DSSPSM) strategy that allows for good soft switching and dynamic response performance in the presence of step variations is presented in this paper. The working principle, soft switching characteristics, and voltage gain formulae of a LLC converter with DSSPSM have been provided separately. Furthermore, the method for realizing DSSPSM is proposed. Specifically, some key components of the proposed DSSPSM are carefully investigated, including a parameter variation analysis, the start-up process, and the zero-crossing capture of the resonant current. The simulation and experiment results verify the feasibility of the proposed control method. It is observed that the zero voltage switching of the switches and the zero current switching of the rectifier diodes can be easily realized in presence of step load variations.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• The Journal of Korean Society for Radiation Therapy
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• v.16 no.2
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• pp.25-32
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• 2004

Purpose : The simulator is used to determine patient field and ensure the treatment field, which encompasses the required anatomy during patient normal movement such as during breathing. The latest simulator provide real time display of still, flouroscopic and digitalized image, but conventional simulator is not yet. The purpose of this study is to introduce digital image capture system(DICS) using conventional simulator and clinical case using digital captured still and flouroscopic image. Methods and materials : We connect the video signal cable to the video terminal in the back up of simulator monitor, and connect the video jack to the A/D converter. After connection between the converter jack and computer, We can acquire still image and record flouroscopic image with operating image capture program. The data created with this system can be used in patient treatment, and modified for verification by using image processing software. (j.e. photoshop, paintshop) Result : DICS was able to establish easy and economical procedure. DCIS image was helpful for simulation. DICS imaging was powerful tool in the evaluation of the department specific patient positioning. Conclusion : Because the commercialized simulator based of digital capture is very expensive, it is not easily to establish DICS simulator in the most hospital. DICS using conventional simulator enable to utilize the practical use of image equal to high cost digitalized simulator and to research many clinical cases in case of using other software program.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.715-720
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• 2016

This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.5
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• pp.817-826
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• 2001

In this paper, we implemented QPSK(Quadrature Phase-Shift Keying) modem which is widely used for communication systems, using a general Digital Signal Processor(DSP), TM320C31. Up to now, almost all of communication systems consist of hardware. However, the implemented system herein is composed of software and hardware part. Software part includes the modulation process, before passing D/A(Digital-to-Analog Converter) and the demodulation process, after passing A/D(Analog-to-Digital Converter) in IF(Intermediate Frequency) node. Hardware part is related to input, output and process of signal. To demonstrate the successful implementation of modem, the output results obtained from DSP processor are compared with the simulated result on the personal computer.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.255-262
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• 2011

This paper proposes a grid-tied power conditioning system for fuel cell, which consists of three-phase current-fed DC-DC converter and three-phase PWM inverter. The three-phase current-fed DC-DC converter boosts fuel cell voltage of 26-48 V up to 400 V with zero-voltage switching (ZVS) scheme, while the three-phase PWM(Pulse Width Modulation) inverter controls the active and reactive power supplied to the grid. The operation of the proposed power conditioning system with fuel cell model is verified through simulations with PSCAD/EMTDC software. The feasibility of hardware implementation is verified through experimental works with a laboratory prototype with 1.2 kW proton exchange membrane (PEM) fuel cell stack. The proposed power conditioning system can be commercialized to interconnect the fuel cell with the power grid.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.1
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• pp.72-81
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• 2009

This paper presents quasi-resonant type high power factor ac power supply for atmospheric pressure plasma cleaning system adopting three phase PFC boost converter and it's control method. The presented ac power supply consists of single phase H-bridge inverter, step-up transformer for generating high voltage and three phase PFC boost converter for high power factor on source utility. Unlikely to the traditional LC resonant converter, the propose one has an inductor inside only. A single resonant takes place through the inside inductor and the capacitor from the plasma load modeled into two series capacitor and one resistance. The quasi-resonant can be achieved by cutting the switching signal when the load current decrease to zero. To obtain power control ability, the propose converter controlled by two control schemes. One is the changing output pulse period scheme in the manner of PFM(Pulse Frequency Modulation) control. On the other, to provide more higher power to load, the DC rail voltage is directly controlled by the 3-phase PFC boost converter. The significant merits of the proposed converter are the uniform power providing capability for high quality plasma generation and low reactive power in AC and DC side. The proposed work is verified through digital simulation and experimental implementation.

• Journal of Sensor Science and Technology
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• v.14 no.4
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• pp.272-277
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• 2005

A CMOS active pixel sensor has been designed and fabricated using standard 2-poly and 4-metal $0.35{\mu}m$ CMOS processing technology. The CMOS active pixel sensor has been made up of a unit pixel having a highly sensitive PMOSFET photo-detector and electronic shutters that can control the light exposure time to the PMOSFET photo-detector, correlated-double sampling (CDS) circuits, and an 8-bit two-step flash analog to digital converter (ADC) for digital output. This sensor can obtain a stable photo signal in a wide range of light intensity. It can be realized with a special function of an electronic shutter which controls the light exposure-time in the pixel. Moreover, this sensor had obtained the digital output using an embedded ADC for the system integration. The designed and fabricated image sensor has been implemented as a $128{\times}128$ pixel array. The area of the unit pixel is $7.60{\mu}m{\times}7.85{\mu}m$ and its fill factor is about 35 %.