• Journal of Communications and Networks
• /
• v.7 no.3
• /
• pp.248-257
• /
• 2005

In this paper, we develop design procedures for carrier tracking loop for orthogonal frequency division multiplexing (OFDM) systems or other systems of blocked data. In such communication systems, phase error measurements are made infrequent enough to invalidate the traditional loop design methodology which is based on analog loop design. We analyze the degradation in the OFDM schemes caused by the tracking loop and show how the performance is dependent on the rms phase error, where we distinguished between the effect of the variance in the average phase over the symbol and the effect of the phase change over the symbol. We derive the optimal tracking loop including optional delay in the loop caused by processing time. Our solution is general and includes arbitrary phase noise apd additive noise spectrums. In order to guarantee a well behaved solution, we have to check the design against margin constraints subject to uncertainties. In case the optimal loop does not meet the required margin constraints subjected to uncertainties, it is shown how to apply a method taken from control theory to find a controller. Alternatively, if we restrict the solution to first or second order loops, we give a simple loop design procedure which may be sufficient in many cases. Extensions of the method are shown for using both pilot symbols and data symbols in the OFDM receiver for phase tracking. We compare our results to other methods commonly used in OFDM receivers and we show that a large improvement can be gained.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.89-90
• /
• 2008

We present an implementation and it's real-sea test of an underwater acoustic communication system, which allows the system to reduce complexity and increase robustness in time variant underwater environments. For easy adaptation to complicated and time-varying environments of the ocean, all-digital transmitter and receiver systems were implemented. For frame synchronization the CAZAC sequence was used, and QPSK modulation/demodulation method with carrier frequency of 25kHz and a bandwidth of 5kHz were applied to generate 10kbps transmission rate including overhead. To improve transmission quality, we used several techniques and algorithms such as adaptive beamforming, adaptive equalizer, and convolution coding/Viterbi decoding. For the verification of the system performance, measurement of BER has been done in a very shallow water with depth of 20m at JangMok, Geoje. During the experiment, image data were successfully transmitted up to about 9.6km.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.9
• /
• pp.903-911
• /
• 2014

This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of $1^{st}$ PLL used as reference frequency of $2^{nd}$ PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5~8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about -3 dBm, the maximum lock-in time and phase noise are within 60 us and -95 dBc/Hz at 10 kHz offset, respectively.

• ETRI Journal
• /
• v.34 no.5
• /
• pp.649-654
• /
• 2012

This paper presents a novel 16-quadrature-amplitude-modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a $0.1{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 21.5 dB.

• Journal of Sensor Science and Technology
• /
• v.20 no.3
• /
• pp.199-206
• /
• 2011

Sell call radio buoy is mostly used for searching for the location of fishing nets. Sell call radio buoy for the detection of the code uses the band pass filter(BPF). All BPF is used by imported from Japanese companies. But, Japanese companies stopped selling buoys for searching for the location of fishing nets, and domestic manufacturing companies could not sell buoys any more. Therefore, In this paper, a new method to replace the conventional buoy code detector is proposed. The proposed methods are constructed with an analog filter division composed of BPFs and notch filters as well as a microprocessor with analog digital converters. The advantage of proposed methods is able to combine various codes, can enhance receiver sensitivity. The experimental results confirm the usefulness of the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.2
• /
• pp.85-90
• /
• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2003.11a
• /
• pp.394-397
• /
• 2003

In this paper, we have proposed a clock recovery algorithm of OFDM/QPSK-DMR(Orthogonal Frequency Division Multiplexing/Quadrature Phase Shift Keying Modulation-Digital Microwave Radio)system using BL-PSF(Band Limited-Pulse Shaping Filter) and have analyzed the clock phase error variance performance of OFDM/QPSK and single carrier DMR systems. The existing OFDM/QPSK-DMR system using the windowing requires training sequence or CP(Cyclic Prefix) to synchronize a receiver clock frequency Because there is no training sequence or CP(Cyclic prefix) in our proposed DMR system, the proposed clock recovery algorithm is useful to the OFDM/QPSK-DMR system using BL-PSF, The simulation results confirm that the proposed clock recovery algorithm has the same clock phase error variance performance in a single carrier DMR system under AWGN(Additive White Gaussian Noise) environment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.11
• /
• pp.1190-1196
• /
• 2014

This paper presents the design of a Frequency Modulated Continuous Wave(FMCW) radar altimeter with wide altitude range and low measurement errors. Wide altitude range is achieved by employing the optic delay in the transmitting path to reduce the dynamic range of measuring altitude. Transmitting power and receiver gain are also controlled to have the dynamic range of the received power be reduced. In addition, low measurement errors are obtained by improving the sweep linearity using the Direct Digital Synthesizer(DDS) and minimizing the phase noise employing the reference clock(Ref_CLK) as the offset frequency of the Phase Locked Loop(PLL).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.8
• /
• pp.784-789
• /
• 2011

In this paper, a tunable integrated transmitter leakage canceller based on an autotransformer for ultra-high-frequency (UHF) RFID readers is presented. The proposed TX leakage canceller consists of an autotransformer, a digital tuning capacitor, a voltage controlled tuning resistor, and a compensating amplifier, and it is designed using 0.13 ${\mu}m$ 1-poly 6-metal RF CMOS process. The simulation results show that the proposed structure has over 55 dB rejection characteristic between a transmitter and a receiver and a 2.5 dB of the RX insertion loss. The TX leakage canceller can be digitally tuned from 825 MHz to 985 MHz with the tuning capacitor and it can be fully integrated.

• Proceedings of the KIEE Conference
• /
• 2007.04a
• /
• pp.289-291
• /
• 2007

The Digital Multimedia Broadcasting(DMB) system is developed to offer high quality audio-visual multimedia contents to the uses by the various portable terminals in the mobile environment. Integrated complex reception platform is required to receive multimedia broadcasting services transmitted from various transmission media. In this paper, we present the design and implementation technic for providing the both of terrestrial and satellite DMB services simultaneously using the same hardware platform. The implemented complex receiving terminal to accommodate these DMB services simultaneously need composed of it RF module. it baseband module, it complex control module and the complex de-multiplexer module. The complex control module is designed using uClinux operating system. The complex de-multiplexer, which perform the functions of the address decoder and each DMB stream de-multiplexer, is implemented. with FPGA device. The implemented platform is tested in a real environment and its performance is satisfied with required performance criteria.