• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• The Journal of the Acoustical Society of Korea
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• v.22 no.8
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• pp.680-686
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• 2003

Digital waveguide model is a general method that is used in physical modeling of musical instruments. Wave motion is analyzed by time or by space in digital waveguide model. Because sampling is made via time, it is general that musical instrument model is described by wave motion of time. In this paper, we synthesized the musical instrument sound by adding instrument body model to the spatial based string model. In this way, we could improve sound quality and process musical instrument model's tone control variables effectively. We explained about delay error that happens in string and body in space based sampling and showed method to process fractional delay using FD (Fractional Delay)filter. Finally, we explained the relation between tone quality and number of delays. And we also compared the result with time base digital waveguide model.

• Journal of Power Electronics
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• v.12 no.4
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• pp.623-631
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• 2012

In this paper, a digital controller design procedure is presented for single-phase voltage-doubler boost rectifiers (VDBR). The model derivation of the single-phase VDBR is performed in the s-domain. After that the simplified equivalent z-domain models are derived. These z-domain models are utilized to design the input current and the output dc-link voltage controllers. For the controller design in the z-domain, the traditional K-factor method is modified by considering the nature of the digital controller. The frequency pre-warping and anti-windup techniques are adapted for the controller design. By using the proposed method, the phase margin and the control bandwidth are accurately achieved as required by controller designers in a practical frequency range. The proposed method is applied to a 2.5 kVA single-phase VDBR for Uninterruptible Power Supply (UPS) applications. From the simulation and the experimental results, the effectiveness of the proposed design method has been verified.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.8
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• pp.80-85
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• 2009

In this paper, we propose a full digital capacitive sensing touch key reducing the effects due to the variations of resistance and clock frequency. The proposed circuit consists of two capacitive loads to measure and a resistor between the capacitive loads. The method measures the delays of the resistor and two capacitive loads, respectively. The ratio of the two delays is represented as the ratio of the two capacitive loads and is irrelative to the resistance and the clock frequency if quantization error is disregarded. Experimental results show the proposed scheme efficiently reduces the effects due to the variations of clock frequency and resistance. Further more the method has 1.04[pF] resolution and can be used as a touch key.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.497-502
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• 2001

We propose a method to represent binary data by modulating both the intensity and the phase of uniform plane waves with a twisted-nematic liquid crystal display for holographic digital data storage especially in a disk-shaped recording medium. As far as intensity modulation is concerned, our method is not different from the conventional method, because binary bit values 0 and 1 are represented by the dark (off) and lit (on) states of the liquid crystal display pixels, respectively (or vice versa). With our method, however, the on pixels are also controlled so that the beams passing through them can have one of two different phase delays. If the difference of the two phase delays is close to 180 degrees, we can reduce the dc component of the data image and thus improve the beam intensity uniformity at the holographic recording plane when Fourier plane holograms are recorded. The feasibility of our method is experimentally demonstrated.

• Korean Journal of Optics and Photonics
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• v.12 no.4
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• pp.339-344
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• 2001

We propose a method to represent binary data by modulating both the intensity and the phase of uniform plane waves with a twisted-nematic liquid crystal display for holographic digital data storage especially in a disk-shaped recording medium. As far as intensity modulation is concerned, our method is not different from the conventional method, because binary bit values 0 and 1 are represented by the dark (off) and lit (on) states of the liquid crystal display pixels, respectively (or vice versa). With our method, however, the on pixels are also controlled so that the beams passing through them can have one of two different phase delays. If the difference of the two phase delays is close to 180 degrees, we can reduce the dc component of the data image and thus improve the beam intensity uniformity at the holographic recording plane when Fourier plane holograms are recorded. The feasibility of our method is experimentally demonstrated. rated.

• Journal of Trauma and Injury
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• v.35 no.2
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• pp.92-98
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• 2022

Purpose: Critically ill patients are frequently transferred from one point of care to a hospital that can provide a higher level of care. To achieve optimal treatment within the targeted window of time necessary for time-sensitive cases like major trauma, rapid transportation and decision making are essential. Transferred patients have often undergone radiologic imaging at the referring hospital. Examining these outside images is paramount. Therefore, this study was conducted to estimate the upload time of outside images. Methods: This retrospective study was conducted from January to April 2020. Patients transferred from other hospitals with digitally recorded CDs or DVDs of radiologic or diagnostic images were included. When the patients were registered at the emergency department reception desk, the digital images were transmitted to our picture archiving and communication system using transmission software. The time of upload and the numbers of digital images were recorded. The time interval from patient registration to the time of upload was calculated. Results: The median number of images was 688 in the trauma team activation (TTA) group (688 in the TTA group, 281 in the non-TTA trauma group, and 176 in the nontrauma group, respectively; P<0.001). The median upload time was 10 minutes. The longest upload time was 169 minutes. The upload time was more than 20 minutes in 12 cases (19.4%). Conclusions: Patients with major trauma bring more images than patients with other diseases. Unexpected delays (>20 minutes) were noted in approximately 20% of cases. It is necessary to minimize this time.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.12
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• pp.10-18
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• 1997

The parallel trabutary signals in the SDH-based transmission system have the frame phase skew due to uneven transmission delays in the data and the clock path. This phase skew must be eliminated prior to synchronously multiplexing process. A new twenty-four channel, 51.84Mb/s DFPA(Digital Frame Phase Aligner) has been designed and fabricated in 0.8.mu.m CMOS gate array. This unique device phase-aligns the skewed input signals with refernce frame synchronous signal and reference clok for subsequent synchronous multiplexing process. the performance of fabricated device is evaluated by the STM-16 transmission system and DS-3 meansurement set. The frame phase margin of +2/-3 bit periods has been demonstrated.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.4
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• pp.151-160
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• 2009

While portable and wireless devices are pouring, a new network technology is needed as a breakthrough. The new network technology features large delays, intermittent connectivity, and absence of an end-to-end path from sources to destinations. A network which has one of those characteristics is called DTNs(Delay Tolerant Networks). The main 4 routing methods have been researched so far in extream environment. In this paper, we look into the reliability of DTMNs(Delay Tolerant Mobile Networks) in several different situations, and propose an algorithm that selects a positive routine by sending the only information of its position when making a connection to a detected node. We simulate the proposed algorithm here in DTN using ONE simulator. As a result, it shows that the algorithm reduces the number of message transmission each node.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1444-1454
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• 2000

The implementation of IF group delay equalizer and its performance are presented for radio relay system applications, and measured results are in good agreement with the simulated ones based upon analytical formulations. For waveguide filter of 40㎒ channel spacing, equalized delay accuracy of about +/- 2.0nsec can be obtained only by constructing 4 stage delay circuits, which provides good performance in system BER curves compared with no filter case, and the difference is less than 1.0㏈ at $10^{-12}$ BER. So this scheme with simple hardware design can be used for correcting the distorted group delays mainly caused by wavegiude filters. To evaluate the designed group delay equalizer, various simulated and experimental results are shown here in conjunction with STM-1 signal of co-channel 64-QAM digital radio relay system.