• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.89-100
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• 1997

This paper investigated a new type of low voltage threshold switch (LVTS). As distinguished from the many other types of electronic threshold switches, the LvTS is ; voltage controlled, occurs at low voltages ($V_{2}$ $O_{5}$lV devices. The average low threshold voltage < $V_{LVT}$>=218 mV (standard deviation =24mV~kT/q, where T=300K), and was independent of the device area (x100) and amorphous oxide occurred in an ~22.angs. thick interphase of the V/amorphous- $V_{2}$ $O_{5}$ contacts. At $V_{LVT}$ there was a transition from an initially low conductance (OFF) state into a succession of quantized states of higher conductance (ON). The OFF state was spatically homogeneous and dominated by tunneling into the interphase. The ON state conductances were consistent with the quantized conductances of ballistic transport through a one dimensional, quantum point contact. The temeprature dependence of $V_{LVT}$, and fit of the material parameters (dielectric function, barrier energy, conductivity) to the data, showed that transport in the OFF and ON states occurred in an interphase with the characteristics of, respectively, semiconducting and metallic V $O_{2}$. The experimental results suggest that the LVTS is likely to be observed in interphases produced by a critical event associated with an inelastic transfer of energy.rgy.y.rgy.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.193-193
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• 2011

To obtain ceramic films, the sol-gel coating technique has been broadly used with heat treatment, but crack formation tend to occur during heat treatment in thick sol-gel films. We prepared PZT thin films by sol-gel method with single-step spin coating process. The PZT solution have been synthesized using lead acetate ($Pb(CH_3COO)_2$), zirconium acetylacetonate ($Zr(OC_3H_7^n)_4$), and titanium diisopropoxide bis(acetylacetonate) 75wt% in isopropanol ($Ti(OC_3H_7^i)_2(OC_3H_7^n)_2$) as starting materials and n-propanol was selected as a solvent. The poly(vynilpyrrolidone) (PVP) was added with 0, 0.25, 0.5, 0.75, and 1 molar ratios to control viscosity of solution. We investigated influence of the viscosity on thickness, microstructure, and electrical properties of final PZT films. Thermo-gravimetric analysis and differential scanning calorimeter (TGA/DSC) was carried out from room temperature to $800^{\circ}C$ in order to measure pyrolysis temperature. Structural characteristics were analyzed by X-ray diffraction (XRD) and scanning electron microscopy (SEM). Ferroelectric and dielectric properties were measured by RT66A (Radiant) and impedance analyzer (Agilent), respectively. The thicknesses of PZT films depended on incorporation of an excess amount of PVP. Finally, we obtained PZT films of good quality without crack formation via single-step spin coating.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.12
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• pp.852-856
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• 2014

$BaTiO_3$ nano powder can be synthesized by hydrate salt method at $120^{\circ}C$ in air. Decreasing the thickness of thick film, the nano dielectric particle is needed in electronic ceramics. However, the synthesis of $BaTiO_3$ nano particle at low temperature in air and their mechanism were not reported enough. And ultrasonic treatment can be tried because of low temperature process in air. Therefore, in this study, the $BaTiO_3$ nano powder was synthesised with the synthesis time and ultrasonic treatment at $120^{\circ}C$ in air. In the synthesis process, the effects of process were evaluated. From the experimental observation, the synthesis mechanism was proposed. The homogeneous $BaTiO_3$ particle was synthesised by KOH salt solution at $120^{\circ}C$ for 1hour. It was conformed that the ultrasonic treatment effected on the increase of synthesis rate. After cutting the salt powder using FIB, $BaTiO_3$ nano particles observed homogeneously in the cross-section of the salt particle.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.4 no.4
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• pp.378-387
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• 1994

To improve the properties of $PbTiO_3$ thin films successfully grown by thermal diffusion of 3 component layers of $Ti0_2/Pb/TiO_2(900{\AA}/900{\AA}/900{\AA})$ in preceding research, 3, 5, 7, 9, and 11 multilayer structures $(TiO_2/Pb/.../Tio_2)$ with thinner component layer of $200~300 {\AA}$ thick were deposited on Si substrate by RF sputtering, which were followed by RTA to form $PbTiO_3$ thin films. As a result, $PbTiO_3$ single phase was formed above $500^{\circ}C$. When the thickness of component layer reduced and the number of component layers increased, suppression of Pb-silicate and voids formation resulted in relatively sharp interfaces and the film composition became more homogeneous. Relative dielectric constants in MIM structure were independent of the annealing condition, but they increased with increasing thickness of the $PbTiO_3$ thin films. The maximum breakdown field in MIS structure reached 150kV/cm.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.9-16
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• 1999

When the conventional IPD (inter-poly-dielctrics) layer with ONO(oxide-nitride-oxide) structure was used in the Flash EEPROM cell, its data retention characteristics were significanfly degraded because the top oxide of the ONO layer was etched off due to the cleaning process used in the gate oxidation process for the peripheral MOSFETs. When the IPD layer with the ONON(oxide-nitride-oxide-nitride) was used there, however, its data retention characteristics were much improved because the top nitride of the ONON layer protected the top oxide from being etched in the cleaning process. For the modelling of the data retention characteristics of the Flash EEPROM cell with the ONON IPD layer, the decrease of the threshold voltage cue to the charge loss during the bake was here given by the empirical relation ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$ and the values of the ${\beta}$=184.7, m=0.224, Ea=0.31 eV were obtained with the experimental measurements. The activation energy of 0.31eV implies that the decrease of the threshold voltage by the back was dur to the movement of the trapped electrons inside the inter-oxide nitride layer. On the other hand, the results of the computer simulation using the model were found to be well consistent with the results of the electrical measurements when the thermal budget of the bake was not high. However, the latter was larger then the former in the case of the high thermal budger, This seems to be due to the leakage current generated by the extraction of the electrons with the bake which were injected into the inter-oxide niride later and were trapped there during the programming, and played the role to prevent the leakage current. To prevent the generation of the leakage current, it is required that the inter-oxide nitride layer and the top oxide layer be made as thin and as thick as possible, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.33-38
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• 2021

Recently, rollable and foldable displays are attracting great attention in the flexible display market due to their excellent form factor. To predict and prevent the mechanical failure of the display panels, it is essential to accurately understand the mechanical properties of brittle SiN_x thin films, which have been used as an insulating film in flexible displays. In this study, tensile properties of the ~130 nm- and ~320 nm-thick SiN_x thin films were successfully measured by coating a ~190 nm-thick organic nano-support-layer (PMMA, PS, P3HT) on the fragile SiN_x thin films and stretching the films as a bilayer state. Young's modulus values of the ~130 nm and ~320 nm SiN_x thin films fabricated through the controlled chamber pressure and deposition power (A: 1250 mTorr, 450 W/B: 1000 mTorr, 600 W/C: 750 mTorr, 700 W) were calculated as A: 76.6±3.5, B: 85.8±4.6, C: 117.4±6.5 GPa and A: 100.1±12.9, B: 117.9±9.7, C: 159.6 GPa, respectively. As a result, Young's modulus of ~320 nm SiN_x thin films fabricated through the same deposition condition increased compared to the ~130 nm SiN_x thin films. The tensile testing method using the organic nano-support-layer was effective in the precise measurement of the mechanical properties of the brittle thin films. The method developed in this study can contribute to the robust design of the rollable and foldable displays by enabling quantitative measurement of mechanical properties of fragile thin films for flexible displays.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.1
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• pp.7-15
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• 2004

The ferroelectric SBT thin films as a material of capacitors for non-volatile FRAMs have some problems that its remanent polarization value is relatively low and the crystallization temperature is quite high abovc 80$0^{\circ}C$. Therefore, in this paper, SBTN solution with S $r_{0.9}$B $i_{2.1}$T $a_{1.8}$N $b_{0.2}$$O_{9}$ composition was synthesized by sol-gel method. Sr(O $C_2$ $H_{5}$)$_2$, Bi(TMHD)$_3$, Ta(O $C_2$ $H_{5}$)$_{5}$and Nb(O $C_2$ $H_{5}$)$_{5}$ were used as precursors, which were dissolved in 2-methoxyethanol. SBTN thin films with 200 nm thickness were deposited on Pt/Ti $O_2$/ $SiO_2$/Si substrates by spin-coating. UV-irradiation in a power of 200 W for 10 min and rapid thermal annealing in a 5-Torr-oxygen ambient at 76$0^{\circ}C$ for 60 sec were used to promote crystallization. The films were well crystallized and fine-grained after annealing at $650^{\circ}C$ in oxygen ambient. The electrical characteristics of 2Pr=11.94 $\mu$C/$\textrm{cm}^2$, Ps＋/Pr＋=0.54 at the applied voltage of 5 V were obtained for a 200-nm-thick SBTN films. This results show that 2Pr values of the UV irradiated and rapid thermal annealed SBTN thin films at the applied voltage of 5 V were about 57% higher than those of no additional processed SBTN thin films. thin films.lms.s.s.

• Journal of the Korean Vacuum Society
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• v.15 no.4
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• pp.395-403
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• 2006

It is known that $MgAl_2O_4$ has higher resistance to moisture than MgO, in humid ambient MgO is chemically unstable. It reacts very easily with moisture in the air. In this study, the characteristic of $MgAl_2O_4$ and $MgAl_2O_4/MgO$ layers as dielectric protection layers for AC- PDP (Plasma Display Panel) have been investigated and analysed in comparison for conventional MgO layers. MgO and $MgAl_2O_4$ films both with a thickness of $1000\AA$ and $MgAl_2O_4/MgO$ film with a thickness of $200/800\AA$ were grown on the Cu substrates using the electron beam evaporation. $1000\AA$ thick aluminium layers were deposited on the protective layers in order to avoid the charging effect of $Ga^+$ ion beam while the focused ion beam(FIB) is being used. We obtained sputtering yieds for the MgO, $MgAl_2O_4$ and $MgAl_2O_4/MgO$ films using the FIB system. $MgAl_2O_4/MgO$ protective layers have been found th show $24{\sim}30%$ lower sputtering yield values from 0.244 up to 0.357 than MgO layers with the values from 0.364 up to 0.449 for irradiated $Ga^+$ ion beam with energies ranged from 10 kV to 14 kV. And $MgAl_2O_4$ layers have been found to show lowest sputtering yield values from 0.88 up to 0.109. Secondary electron emission coefficient(g) using the ${\gamma}$- FIB. $MgAl_2O_4/MgO$ and MgO have been found to have similar g values from 0.09 up to 0.12 for indicated $Ne^+$ ion with energies ranged from 50 V to 200 V. Observed images for the surfaces of MgO and $MgAl_2O_4/MgO$ protective layers, after discharge degradation process for 72 hours by SEM and AFM. It is found that $MgAl_2O_4/MgO$ protective layer has superior hardness and degradation resistance properties to MgO protective layer.