• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.4 s.37
• /
• pp.331-338
• /
• 2005

The rapid advances in high power light sources and arrays as encountered in incandescent lamps have induced dramatic increases in die heat flux and power consumption at all levels of high power LED packaging. The lifetime of such devices and device arrays is determined by their temperature and thermal transients controlled by the powering and cooling, because they are usually operated under rough environmental conditions. The reliability of packaged electronics strongly depends on the die attach quality, because any void or a small delamination may cause instant temperature increase in the die, leading sooner or later to failure in the operation. Die attach materials have a key role in the thermal management of high power LED packages by providing the low thermal resistance between the heat generating LED chips and the heat dissipating heat slug. In this paper, thermal transient characteristics of die attach in high power LED package have been studied based on the thermal transient analysis using the evaluation of the structure function of the heat flow path. With high power LED packages fabricated by die attach materials such as Ag paste, solder paste and Au/Sn eutectic bonding, we have demonstrated characteristics such as cross-section analysis, shear test and visual inspection after shear test of die attach and how to detect die attach failures and to measure thermal resistance values of die attach in high power LED package. From the structure function oi the thermal transient characteristics, we could know the result that die attach quality of Au/Sn eutectic bonding presented the thermal resistance of about 3.5K/W. It was much better than those of Ag paste and solder paste presented the thermal resistance of about 11.5${\~}$14.2K/W and 4.4${\~}$4.6K/W, respectively.

• Journal of Sensor Science and Technology
• /
• v.31 no.6
• /
• pp.361-365
• /
• 2022

Advanced packaging demands are driven by the need for dense integration systems. Consequently, stacked packaging technology has been proposed instead of reducing the ultra-fine patterns to secure economic feasibility. This study proposed an effective packaging process technology for semiconductor devices using a 9-inch dicing die attach film (DDAF), wherein the die attach and dicing films were combined. The process involved three steps: tape lamination, dicing, and bonding. Following the grinding of a silicon wafer, the tape lamination process was conducted, and the DDAF was arranged. Subsequently, a silicon wafer attached to the DDAF was separated into dies employing a blade dicing process with a two-step cut. Thereafter, one separated die was bonded with the other die as a substrate at 130 ℃ for 2 s under a pressure of 2 kgf and the chip was hardened at 120 ℃ for 30 min under a pressure of 10 kPa to remove air bubbles within the DAF. Finally, a curing process was conducted at 175 ℃ for 2 h at atmospheric pressure. Upon completing the manufacturing processes, external inspections, cross-sectional analyses, and thermal stability evaluations were conducted to confirm the optimality of the proposed technology for application of the DDAF. In particular, the shear strength test was evaluated to obtain an average of 9,905 Pa from 17 samples. Consequently, a 3D integration packaging process using DDAF is expected to be utilized as an advanced packaging technology with high reliability.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.1
• /
• pp.1-7
• /
• 2020

The backside metallization process is typically used to attach a chip to a lead frame for semiconductor packaging because it has excellent bond-line and good electrical and thermal conduction. In particular, the backside metal with the Ag/Sn/Ag sandwich structure has a low-temperature bonding process and high remelting temperature because the interfacial structure composed of intermetallic compounds with higher melting temperatures than pure metal layers after die attach process. Here, we introduce a die attach process with the Ag/Sn/Ag sandwich structure to apply commercial semiconductor packages. After the die attachment, we investigated the evolution of the interfacial structures and evaluated the shear strength of the Ag/Sn/Ag sandwich structure and compared to those of a commercial backside metal (Au-12Ge).

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.21 no.12
• /
• pp.261-267
• /
• 2020

The demand for faster, lighter, and thinner portable electronic devices has brought about a change in semiconductor packaging technology. In response, a stacked chip-scale package(SCSP) is used widely in the assembly industry. One of the key materials for SCSP is a die-attach film (DAF). Excellent flowability is needed for DAF for successful die attachment without voids. For DAF with high flowability, two-step curing is often required to reduce a cure crack, but one-step curing is needed to reduce the processing time. In this study, DAF composition was categorized into three groups: cure (epoxy resins), soft (rubbers), hard (phenoxy resin, silica) component. The effect of the composition on a cure crack was examined when one-step curing was applied. The die-attach void and flowability were also assessed. The cure crack decreased as the amount of hard components decreased. Die-attach voids also decreased as the amount of hard components decreased. Moreover, the decrease in cure component became important when the amount of hard component was small. The flowability was evaluated using high-temperature storage modulus and bleed-out. A decrease in the amount of hard components was critical for the low storage modulus at 100℃. An increase in cure component and a decrease in hard component were important for the high bleed-out at 120℃(BL-120).

• Proceedings of the Korea Inteligent Information System Society Conference
• /
• 2001.01a
• /
• pp.224-229
• /
• 2001

When a semiconductor package is assembled, various materials such as die attach adhesive, lead frame, EMC (Epoxy Molding Compound), and gold wire are used. For better preconditioning performance, the combination between the packaging materials by studying the compatibility of their properties as well as superior packaging material selection is important. But it is not an easy task to find proper packaging material sets, since a variety of factors like package design, substrate design, substrate size, substrate treatment, die size, die thickness, die passivation, and customer requirements should be considered. This research applies case-based reasoning(CBR) technique to solve this problem, utilizing prior cases that have been experienced. Our particular interests lie in building decision support model to aid the selection of proper die attach adhesive. The preliminary results show that this approach is promising.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.390-391
• /
• 2007

LED Packaging 과정 중 Die bond 재료로 Silver epoxy를 사용하여 Packaging 한 후 T3Ster 장비로 열 저항 값(Rth)을 측정하였다. Silver epoxy 의 접착 두께를 조절하여 열 저항 값을 측정하였고, 열전도도 값이 다른 Silver epoxy를 사용하여 열 저항 값을 측정하였다. Silver epoxy 접착 두께가 충분하여 Chip 전면에 고루 분포되었을 경우 그렇지 않은 경우보다 평균 4.8K/W 낮은 13.23K/W의 열 저항 값을 나타내었고, 열전도도가 높은 Silver epoxy 일수록 열전도도가 낮은 재료보다 평균 4.1K/W 낮은 12K/W의 열 저항 값을 나타내었다.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.2
• /
• pp.65-70
• /
• 2014

Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The $100{\mu}m$-thick PCB substrate exhibited a warpage of $136{\sim}214{\mu}m$. The specimen formed by mounting a $40{\mu}m$-thick Si chip to such a PCB using a die attach film exhibited the warpage of $89{\sim}194{\mu}m$, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a $40{\mu}m$-thick chip to such a PCB possessed the warpage of $-199{\sim}691{\mu}m$, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of $-79{\sim}202{\mu}m$ and $-117{\sim}159{\mu}m$, respectively.

• Korean Journal of Materials Research
• /
• v.19 no.5
• /
• pp.288-292
• /
• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.20 no.4
• /
• pp.503-509
• /
• 2019

The demand for smaller, faster, and multi-functional mobile devices in increasing at a rapidly increasing rate. In response to these trends, Stacked Chip Scale Package (SCSP) is used widely in the assembly industry. A film type adhesive called die attach film (DAF) is used widely for bonding chips in SCSP. The DAF requires high flowability at high die attachment temperatures for bonding chips on organic substrates, where the DAF needs to feel the gap depth, or for bonding the same sized dies, where the DAF needs to penetrate bonding wires. In this study, the mixture design of experiment (DOE) was performed for three raw materials to obtain the optimized DAF recipe for low elastic modulus at high temperature. Three components are acrylic polymer (SG-P3) and two solid epoxy resins (YD011 and YDCN500-1P) with different softening points. According to the DOE results, the elastic modulus at high temperature was influenced greatly by SG-P3. The elastic modulus at $100^{\circ}C$ decreased from 1.0 MPa to 0.2 MPa as the amount of SG-P3 was decreased by 20%. In contrast, the elastic modulus at room temperature was dominated by YD011, an epoxy with a higher softening point. The optimized DAF recipe showed approximately 98.4% pickup performance when a UV dicing tape was used. A DAF crack that occurred in curing was effectively suppressed through optimization of the cure accelerator amount and two-step cure schedule. The imizadole type accelerator showed better performance than the amine type accelerator.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1998.08a
• /
• pp.102-102
• /
• 1998