Browse > Article
http://dx.doi.org/10.5762/KAIS.2020.21.12.261

Effect of Die Attach Film Composition for 1 Step Cure Characteristics and Thermomechanical Properties  

Sung, Choonghyun (Polymeric Materials Engineering Major, Dong-eui University)
Publication Information
Journal of the Korea Academia-Industrial cooperation Society / v.21, no.12, 2020 , pp. 261-267 More about this Journal
Abstract
The demand for faster, lighter, and thinner portable electronic devices has brought about a change in semiconductor packaging technology. In response, a stacked chip-scale package(SCSP) is used widely in the assembly industry. One of the key materials for SCSP is a die-attach film (DAF). Excellent flowability is needed for DAF for successful die attachment without voids. For DAF with high flowability, two-step curing is often required to reduce a cure crack, but one-step curing is needed to reduce the processing time. In this study, DAF composition was categorized into three groups: cure (epoxy resins), soft (rubbers), hard (phenoxy resin, silica) component. The effect of the composition on a cure crack was examined when one-step curing was applied. The die-attach void and flowability were also assessed. The cure crack decreased as the amount of hard components decreased. Die-attach voids also decreased as the amount of hard components decreased. Moreover, the decrease in cure component became important when the amount of hard component was small. The flowability was evaluated using high-temperature storage modulus and bleed-out. A decrease in the amount of hard components was critical for the low storage modulus at 100℃. An increase in cure component and a decrease in hard component were important for the high bleed-out at 120℃(BL-120).
Keywords
Adhesive Film; Die Attach Film; Epoxy; Film-Over-Wire; Cure Crack; Stack-CSP;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 B. Bottoms, M. Tsuriya, C. Richardson, "iNEMI packaging technology roadmap highlights", Proceedings of 2014 International Conference on Electronics Packaging, Toyama, Japan, pp. 188-192, April, 2014. DOI: https://doi.org/10.1109/ICEP.2014.6826686   DOI
2 S. Olson, K. Hummler and B. Sapp, "Challenges in thin wafer handling and processing", Proceedings ofASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference, Saratoga Springs, NY, USA, pp. 62-65, May, 2013 DOI: https://doi.org/10.1109/ASMC.2013.6552776   DOI
3 BK. Appelt, A. Tseng, CH Chen, YS Lai, "Fine pitch copper wire bonding in high volume production", Microelectronics Reliability, Vol. 51, Iss. 1, pp. 13-20, 2011. DOI: https://doi.org/10.1016/j.microrel.2010.06.006   DOI
4 SC Chong, DHS Wee, VS Rao, NS. Vasaria, "Developement of package-on-package using embedded wafer-level package approach", IEEE Transcations on Components Packaging and Manufacturing Technology, Vol. 3, No. 10, pp. 1654-1662, 2013. DOI: https://doi.org/10.1109/TCPMT.2013.2275009   DOI
5 CT. Ko, KN Chen, "Wafer-level bonding/stacking technology for 3D integration", Microelectronics Reliability, Vol. 50, Iss. 4, pp. 481-488, 2010. DOI: https://doi.org/10.1016/j.microrel.2009.09.015   DOI
6 S. Yoshida, G. Fukuda, T. Noji, Y. Kobayashi, S. Kawasaki, "Ka-band 2-stacked chip-scale-package using GaAs PA MMIC with hot-via interconnections for spacecraft applications", Proceedings of 2013 European Microwave Conference, Nuremberg, Germany, pp. 223-226, October, 2013.
7 JH Lau, "Overview and outlook of through-silicon via (TSV) and 3D integrations", Microelectronics International, Vol. 28, Iss. 2, pp. 8-22, 2011. DOI: https://doi.org/10.1108/13565361111127304   DOI
8 X. Zhang, JH. Lau, C. S. Premachandran, SC Chong, LC Wai, "Development of a Cu/low-k stack die fine pitch ball grid array (FBGA) package for system in package applications", IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 1, No. 3, pp. 299-309, 2011. DOI: https://doi.org/10.1109/TCPMT.2010.2100292   DOI
9 S. Priyabadini, T. Sterken, L. Van Hoorebeke, J. Vanfleteren, "3-D stacking of ultrathin chip packages: an innovative packaging and interconnection technology", IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 3, No. 7, pp. 1114-1122, 2013. DOI: https://doi.org/10.1109/TCPMT.2012.2234830   DOI
10 B. H. Oh, H. Y. Loo, P. T. Oh and E. K. Lee, "Challenges in Stacked CSP Packaging Technology," Proceedings of International Conference on Electronic Materials and Packaging, Kowloon, China, pp. 1-4, December, 2006. DOI: https://doi.org/10.1109/EMAP.2006.4430609   DOI
11 M. Karnezos, "3D packaging: where all technologies come together", Proceedings of EIEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium, San Jose, CA, USA, pp. 64-67, July, 2004. DOI: https://doi.org/10.1109/IEMT.2004.1321633   DOI
12 S. R. Vempati, N. Su, CH Khong, YY Lim, K. Vaidyanathan, "Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects", Proceedings of 2009 59th Electronic Components and Technology Conference, San Diego, CA, USA, pp. 980-987, June 2009. DOI: https://doi.org/10.1109/ECTC.2009.5074132   DOI
13 J. Liang, C. Ku and C. Chung, "Applications of film over wire and die attached film in a stacked chip scale package", Proceedings of 2006 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), Taipei, pp. 289-292, October, 2016. DOI: https://doi.org/10.1109/IMPACT.2016.7800052   DOI
14 L. Chen, J. Adams, HW Chu and X. Fan, "Modeling of moisture over-saturation and vapor pressure in die-attach film for stacked-die chip scale packages", Journal of Materials Science: Materials in Electronics, Vol 27, Iss. 1, pp. 481-488, 2016. DOI: https://doi.org/10.1007/s10854-015-3778-5   DOI
15 HH. Ren, XS. Wang, S. Jia, "Fracture analysis on die attach adhesives for stacked packages based on in-situ testing and cohesive zone model", Microelectronics Reliability, Vol. 53, Iss. 7, pp. 1021-1028, 2013. DOI: https://doi.org/10.1016/j.microrel.2013.04.001   DOI
16 N. Ye, Q. Li, H. Zhang, Z. Ji, X. Yang, CT. Chiu, H. Takiar, "Challenges in assembly and reliability of thin NAND memory die", Proceedings of 2016 IEEE 66th Electronic Components and Technology Conference, Las Vegas, NV, USA, pp. 1840-1846, May, 2016, DOI: https://doi.org/10.1109/ECTC.2016.226   DOI
17 BU. Kang, "Interfacial fracture behavior of epoxy adhesive for electronic components", Journal of the Korea Academia-Industrial, Vol. 12, No. 3, pp. 1479-1487, 2011. DOI: https://doi.org/10.5762/KAIS.2011.12.3.1479   DOI
18 SN, Song, HH. Tan, PL. Ong, "Die attach film application in multi die stack package", Proceedings of 2005 7th Electronics Packaging Technology Conference, Singapore, pp. 848-852, December, 2005. DOI: https://doi.org/10.1109/EPTC.2005.1614517   DOI
19 CL. Chung, CW. Ku, HC. Hsu and SL. Fu, "Comparison between die attach film (DAF) and film over wire (FOW) on stack-die CSP application", Proc. of 2009 European Microelectronics and Packaging Conference, pp. 1-3, Rimini, Italy, 2009.
20 C. Sung, "Optimization of elastic modulus and cure characteristics of composition for die attach film", Journal of the Korea Academia-Industrial, Vol. 20, No.4, pp 503-509, 2019. DOI: https://doi.org/10.5762/KAIS.2019.20.4.503   DOI