• Smart Structures and Systems
• /
• v.26 no.5
• /
• pp.605-617
• /
• 2020

In this study, the experimental tests for the direct tensile strength measurement of Ultra-High Performance Concrete (UHPC) were numerically modeled by using the discrete element method (circle type element) and Finite Element Method (FEM). The experimental tests used for the laboratory tensile strength measurement is the Compressive-to-Tensile Load Conversion (CTLC) device. In this paper, the failure process including the cracks initiation, propagation and coalescence studied and then the direct tensile strength of the UHPC specimens measured by the novel apparatus i.e., CTLC device. For this purpose, the UHPC member (each containing a central hole) prepared, and situated in the CTLC device which in turn placed in the universal testing machine. The direct tensile strength of the member is measured due to the direct tensile stress which is applied to this specimen by the CTLC device. This novel device transferring the applied compressive load to that of the tensile during the testing process. The UHPC beam specimen of size 150 × 60 × 190 mm and internal hole of 75 × 60 mm was used in this study. The rate of the applied compressive load to CTLC device through the universal testing machine was 0.02 MPa/s. The direct tensile strength of UHPC was found using a new formula based on the present analyses. The numerical simulation given in this study gives the tensile strength and failure behavior of the UHPC very close to those obtained experimentally by the CTLC device implemented in the universal testing machine. The percent variation between experimental results and numerical results was found as nearly 2%. PFC2D simulations of the direct tensile strength measuring specimen and ABAQUS simulation of the tested CTLC specimens both demonstrate the validity and capability of the proposed testing procedure for the direct tensile strength measurement of UHPC specimens.

• The Magazine of the IEIE
• /
• v.42 no.7
• /
• pp.45-53
• /
• 2015

Power 소자 기술은 digital & mixed signal device와 on-chip 구현을 위해서 CMOS 공정에 대한 기본 이해가 필요하다. CMOS 공정 기반 위에 power device 공정을 추가하면서 다양한 operation voltage의 power 소자를 구현하고, passive device 들을 동일 공정에서 구현하여 다양한 components 들로 power IC 제품을 design 할 수 있도록 modular process를 제공하는 것이 중요하다. 또한 power device로 주로 사용되는 LDMOS 소자에 대한 performance 개선을 위해 simulation을 통해 key device parameter들의 특성을 예측하고, 구조를 설계하는 것이 Si process 전에 중요한 일 중의 하나이다. 아울러 power management가 potable power, consumer electronics 및 green energy에서 가장 빠르게 성장하는 분야이므로, 차별화된 power 소자 기술을 확보하여 급변하는 시장 환경에 대응하는 것이 필요하다.

• Journal of international Conference on Electrical Machines and Systems
• /
• v.2 no.4
• /
• pp.441-446
• /
• 2013

A thermal model of power modules based on the physical dimension and thermal properties is proposed in this paper. The heat path in the power module is considered as a one-dimensional heat transfer in the model. The method of the parameters extraction for the model is given in the paper. With high speed and accuracy, the thermal model is suit for electrothermal simulation. The proposed model is verified by experimental results.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.5
• /
• pp.500-510
• /
• 2013

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

• Journal of the Semiconductor & Display Technology
• /
• v.14 no.2
• /
• pp.41-45
• /
• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1994.11a
• /
• pp.210-215
• /
• 1994

In the CMOS device, Counter doping is needed to adjust threshold voltage because of the difference between n-MOSFET and p-MOSFET well doping concentration when n+ polysilicon gate is used. Therefore buried channel is formed in the p-channel MOSFET degrading properties. So well doping concentration and doping condition should be considered in fabrication process and device design. Here we are to extract the initial process condition using simulation and fabricate p-MOSFET device and then compare the subthreshold characteristics of simulated and fabricated device.

• Journal of Korean Vacuum Science & Technology
• /
• v.3 no.1
• /
• pp.1-9
• /
• 1999

This paper presents a newly enhanced damage model in Monte Carlo (MC) simulation for the accurate prediction of 3-Dimensional (3D) as-implanted impurity and point defect profiles induced by ion implantation in (100) crystal silicon. An empirical electronic energy loss model for B, BF2, As, P and Si self implant over the wide energy range has been proposed for the ULSI device technology and development. Our model shows very good agreement with the SIMS data over the wide energy range. In the damage accumulation, we considered the self-annealing effects by introducing our proposed non-linear recomvination probability function of each point defect for the computational efficiency. For the damage profiles, we compared the published RBS/channeling data with our results of phosphorus implants. Our damage model shows very reasonable agreement with the experiments for phosphorus implants.

• Journal of the Korean Vacuum Society
• /
• v.16 no.4
• /
• pp.273-278
• /
• 2007

For the simulation of active region in the quantum cascade lasers (QCL), we solved Schrodinger equation utilizing Runge-Kutta method and Shotting method. Wavelength, phonon resonant energy, and dipole matrix element were simulated with the variation of active region thickness. As a result of such simulation, it was suggested the tolerance range of epi-layer thickness error when 3-quantum well QCL structures are grown.

• Journal of the Semiconductor & Display Technology
• /
• v.13 no.4
• /
• pp.55-58
• /
• 2014

The next-generation AlGaN/GaN HEMT power devices need higher power at higher frequencies. To know the device characteristics, the simulation of those devices are made. This paper presents a simulation study on the DC and RF characteristics of AlGaN/GaN HEMT power devices. According to the reduction of gate length from $2.0{\mu}m$ to $0.1{\mu}m$, the simulation results show that the drain current at zero gate voltage increases, the gate capacitance decreases, and the maximum transconductance increases, and thus the cutoff frequency and the maximum oscillation frequency increase. The maximum oscillation frequency maintains higher than the cutoff frequency, which means that the devices are useful for power devices at very high frequencies.

• Journal of the Korean Institute of Plant Engineering
• /
• v.23 no.4
• /
• pp.21-27
• /
• 2018

This paper proposed the real-time monitoring methodology of a traffic signal controller. The proposed methodology is based on the simulation technology, and it is necessary to construct a simulation model imitating the behavior of a traffic signal controller. By executing the simulation model, we can obtain the 'nominal system trajectory' of the traffic signal controller. On the other hand, an IoT(Internet of Things)-based monitoring device is implemented in a traffic signal controller. Through the monitoring device, it is possible to obtain the 'actual system trajectory'. By comparing the nominal system trajectory and the actual system trajectory, we can estimate the degree of deterioration of a traffic signal controller.