• 마이크로전자및패키징학회지
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• 제23권4호
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• pp.25-29
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• 2016

The semiconductor industry has been developed mainly by micronization process due to many advantages of miniaturization of devices. Mass production of semiconductors of 10 nm class has been started recently, and it is expected that the technology generation of 5 nm & 7 nm technology will come. However, excessive linewidth reduction affects physical limits and device reliability. To solve these problems, new process technology development and new concept devices are being studied. In this review, we introduce the next generation technology and introduce the advanced research for the new concept device.

• 전자공학회논문지D
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• 제34D권2호
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• pp.1-9
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• 1997

For the reduction of parasitic inductance and matching of bonding wire in the package of microwave devices, we propose multiple bonding wires buried in a dielectric material of FR-4 composite. This structure is analyzed using the method of moments (MoM) and compared with the common bondwires and ribbon interconnections. The FR-4 composite is modelled by the cole-cole model which can consider the loss and the variation of the permittivity in a frequency. At 20 GHz, the parasitic reactance is reduced by 90%, 80%, 60% compared to those of a single bonding wire in air, double bonding wires in air and ribbon interconnection in air, respectively. Also, the new bondwire shows very good matching of 60.ohm characteristic impedance and has 15dB, 10dB, 5dB improvement of the return loss and 2.5dB, 0.7dB, 0.2dB improvement of the insertion loss compared to the common interconnections. This technique can minimize the parasitic effect of bondwires in microwave device packaging.

• 한국재료학회지
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• 제17권7호
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• ETRI Journal
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• 제33권4호
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• pp.645-647
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• 2011

In this study, a microcapillary pumped loop (MCPL) that can be used as a cooling device for small electronic and telecommunications equipment has been developed. For thin devices such as an MCPL, securing a vapor flow space is a critical issue for enhancing the thermal performance. In this letter, such enhancement in thermal performance was accomplished by eliminating condensed droplets from the vapor line. By fabricating the grooves in the vapor line to eliminate droplets, a decrease in thermal resistance of about 63.7% was achieved.

• 한국산업융합학회 논문집
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• 제27권1호
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• pp.71-76
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• 2024

Automatic production systems are constantly advancing technologies to improve productivity and safety. Specifically, liquid filling machines are primarily utilized to package products into drums after manufacturing process in the hazardous chemical industry. Most existing filling machines allow the operator to open the drum cap and inject the product directly or semi-automation. In this study, we have developed a cap opening and closing mechanism onto the existing drum filling machine, enabling automatic and safe cap manipulation while filling the product in the IBC tank. By applying the appropriate torque value through numerical analysis, we confirmed that the system worked without any problems during the process of opening and closing the cap. Therefore, it is expected that the developed machine will give more production and reduce human efforts without risk in the chemical packaging industry.

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

• 마이크로전자및패키징학회지
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• 제10권4호
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• pp.53-60
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• 2003

CCD(Charge-Coupled Device) wafer와 같이 표면이 polymer 성분의 micro lens로 구성되어있는 경우 passivation 막을 도포하지 않는 것이 보통인데, 이때 particle이 lens 표면에 쉽게 달라붙는 현상이 나타나게 된다. 특히 sawing 하면서 발생하는 particle은 치명적인 불량을 유발한다. 본 연구에서는 sawing에서 발생한 particle을 효과적으로 flushing하기위한 방안으로 측면노즐과 중심노즐의 분사위치, 분사각도, 퍼짐각도를 최적화 하고, 아울러 flushing 노즐을 추가한 새로운 형태의 wafer saw를 도입하였다. 개선된 saw를 적용하여 실험한 결과 particle로 인한 CCD chip의 불량률이 9.l%로부터 0.63%로 현격하게 개선되었음을 확인할 수 있었다.

• 마이크로전자및패키징학회지
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• 제23권4호
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• pp.19-24
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• 2016

Along the few nano sizing dimensions of integrated circuit (IC) devices, acceptable interlayer material for design is inevitable. The interlayer which include dielectric, interconnect, barrier etc. needs to achieve not only electrical properties, but also mechanical properties for endure post manufacture process and prolonging life time. For developing intermetallic dielectric (IMD) the mechanical issues with post manufacturing processes were need to be solved. For analyzing specific structural problem and material properties Raman spectroscopy was performed for various researches in Si semiconductor based materials. As improve of the laser and charge-coupled device (CCD) technology the total effectiveness and reliability was enhanced. For thin film as IMD developed material could be analyzed by Raman spectroscopy, and diverse researches of developing method to analyze thin layer were comprehended. Also In-situ analysis of Raman spectroscopy is introduced for material forming research.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.109-119
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• 2003

o In order to start SIP Project .Marketing (& ASIC team) should present biz planning, schedule, device/SIP specs., in SIP TFT prior to request SIP development for package development project. .In order to prevent (PCB) revision, test, burn-in, & quality strategy should be fixed by SIP TFT (PE/Test, QA) prior to request for PKG development. .Target product price/cost, package/ test cost should be delivered and reviewed. o Minimum Information for PCB Design, Package Size, and Cost .(Required) package form factor: size, height, type (BGA, QFP), Pin count/pitch .(Estimated) each die size including scribe lane .(Estimated) pad inform. : count, pitch, configuration(in-line/staggered), (open) size .(Estimated) each device (I/O & Core) power (especially for DRAM embedded SIP) .SIP Block diagram, and net-list using excel sheet format o Why is the initial evaluation important\ulcorner .The higher logic power resulted in spec. over of DRAM Tjmax. This caused business drop longrightarrow Thermal simulation of some SIP product is essential in the beginning stage of SIP business planning (or design) stage. (i.e., DRAM embedded SIP) .When SIP is developed using discrete packages, the I/O driver Capa. of each device may be so high for SIP. Since I/O driver capa. was optimized to discrete package and set board environment, this resulted in severe noise problem in SIP. longrightarrow In this case, the electrical performance of product (including PKG) should have been considered (simulated) in the beginning stage of business planning (or design).

• 마이크로전자및패키징학회지
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• 제28권4호
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• pp.51-55
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• 2021

본 논문은 보통 병원에서 간호사가 수작업으로 진행하는 약물주입 과정을 대신할 수 있는 의료용 미세 유량 제어 장치를 소개한다. 이는 아두이노로 구현되었으며 환자의 지속적인 관리에 도움이 되고자 한다. 기본적으로 연동펌프를 통해 약물이 주입되며 RGB color sensor를 통해 배출액의 색상을 값으로 받아들이고 이 값을 바탕으로 수액백에 달린 연동펌프의 모터 속도를 조절하는 알고리즘을 아두이노 코딩을 통해 구현한다. 전체적인 시스템은 배터리를 통해 작동되며 연구실에서 355nm UV pulsed laser를 통해 제작한 LIG strain sensor의 추가를 통해 수액백으로부터 주입되는 약물의 양을 측정한다. 이렇게 제작된 미세 유량 제어 장치는 모든 과정을 수작업으로 진행해오던 병원에 곧장 사용 가능하며 간호사의 편의를 제공하고자 한다. 이 장치를 통해 한층 향상된 의료서비스를 제공할 수 있다.