• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.11-14
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• 2022

In this work, we evaluated the Al₂O₃ film, which was deposited by atomic layer deposition, degraded by exposure to harsh environments. The Al₂O₃ films deposited by atomic layer deposition have long been used as a gas diffusion barrier that satisfies barrier requirements for device reliability. To investigate the barrier and mechanical performance of the Al₂O₃ film with increasing temperature and relative humidity, the properties of the degraded Al₂O₃ film exposed to the harsh environment were evaluated using electrical calcium test and tensile test. As a result, the water vapor transmission rate of Al₂O₃ films stored in harsh environments has fallen to a level that is difficult to utilize as a barrier film. Through water vapor transmission rate measurements, it can be seen that the water vapor transmission rate changes can be significant, and the environment-induced degradation is fatal to the Al₂O₃ thin films. In addition, the surface roughness and porosity of the degraded Al₂O₃ are significantly increased as the environment becomes severer. the degradation of elongation is caused by the stress concentration at valleys of rough surface and pores generated by the harsh environment. Becaused the harsh envronment-induced degradation convert amorphous Al₂O₃ to crystalline structure, these encapsulation properties of the Al₂O₃ film was easily degraded.

• Journal of Astronomy and Space Sciences
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• v.24 no.4
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• pp.451-456
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• 2007

Data coming from devices shall be transported to a specific task to be used in a software with the most accurate time and data integrity. During this process, a potential cause for invoking structured hazard and performance degradation is dormant. In this paper, a method which can protect the data integrity from the possible data corruption when collision has happened during I/O data exchange between device and tasks is presented. Also, an example diagram of mechanism according to the method is shown and the effect, merits and demerits of the method is evaluated.

• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.186-188
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• 2003

The ZnO surge arrester is the protective device for limiting surge voltages on equipment by diverting surge current and returning the device to its original status. The occurrence of overvoltage appears in any phase to AC power supply system and it appears in mixing AC and impulse voltages, moreover because HVDC power supply system uses converter in semiconductor, it makes mixed DC and high harmonics voltages. In this study, the various mixed AC and DC voltages was made for investigating the degradation effect of ZnO arrester according to mixed voltage. As a result, the increase of DC component to mixed voltages causes the increase of resistive component of total leakage current to ZnO block. In changing V-I curve for mixed voltages, the cross-over point acts a factor as making the proper capacitor size of an equivalent circuit for ZnO block.

• KIISE Transactions on Computing Practices
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• v.23 no.2
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• pp.134-139
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• 2017

The existing screen mirroring systems are vulnerable to packet loss and inefficient for mobile devices with limited energy capacity. To overcome these problems, we propose a packet loss robust and energy efficient screen mirroring system for mobile device. The proposed system employs systematic Raptor codes for a forward error correction method to mitigate the video quality degradation that is caused by packet loss over wireless networks. For the mobile device energy saving, the proposed system shapes the screen mirroring traffic and adjusts the Raptor encoding parameters. In this paper, the proposed system is fully implemented on single board computers and is examined in a real Wi-Fi Direct network.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• Journal of the Korean Society of Propulsion Engineers
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• v.24 no.2
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• pp.14-27
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• 2020

Differential scanning calorimetry and numerical analysis were performed to estimate the performance degradation and ignition characteristics of the pyrotechnic device due to aging. The reaction kinetics extracted from the calorimetry are implemented into the numerical simulation of the igniter and the pyrotechnic delay, subjected to natural, thermal, and hygrothermal aging conditions. Also, combustion experiments are conducted to confirm that aging due to moisture is a major cause of performance failure of the pyrotechnic device as shown from the present numerical simulations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.143-149
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• 2018

It has become ever harder to design reliable circuits with each nanometer technology node; under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Therefore, circuit designers need to consider these reliability effects in the early stages of design to make sure there are enough margins for circuits to function correctly over their entire lifetime. However, such an approach excessively increases the size and power dissipation of a system. As the impact of reliability, new techniques in designing aging-resilient circuits are necessary to reduce the impact of the aging stresses on performance, power, and yield or to predict the failure of a system. Therefore, in this paper, a novel low power on-chip self-tuning circuit considering the aging effects has been proposed.

• Journal of information and communication convergence engineering
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• v.11 no.4
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• pp.288-292
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• 2013

In this paper, a carbon implant is investigated in detail from the perspectives of performance advantages and side effects for the thick n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET). Threshold voltage ($V_{th}$) adjustment using a carbon implant significantly improves the $V_{th}$ mismatch performance in a thick (3.3-V) n-MOS transistor. It has been reported that a bad mismatch occurs particularly in the case of 0.11-${\mu}m$ $V_{th}$ node technology. This paper investigates a carbon implant process as a promising candidate for the optimal $V_{th}$ roll-off curve. The carbon implant makes the $V_{th}$ roll-off curve perfectly flat, which is explained in detail. Further, the mechanism of hot carrier injection lifetime degradation by the carbon implant is investigated, and new process integration involving the addition of a nitrogen implant in the lightly doped drain process is offered as its solution. This paper presents the critical side effects, such as Isub increases and device performance shifts caused by the carbon implant and suggests an efficient method to avoid these issues.

• Korean Journal of Remote Sensing
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• v.18 no.2
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• pp.91-96
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• 2002

The performance characteristics of a satellite imager using a Time Delay and Integration(TDI) Charge Coupled Device (CCD) with fixed integration time is investigated for the variation of satellite altitude and tilt angle. In consequence of the investigation TDI synchronization using tilt imaging is proposed as a solution to compensate geometric performance degradation due to altitude decrease. The tilt angle optimized for the TDI synchronization at decreased altitude is presented. This result can be used for a TDI CCD imager with variable integration time in a certain range as well.