• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
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• pp.186-188
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• 2003

The ZnO surge arrester is the protective device for limiting surge voltages on equipment by diverting surge current and returning the device to its original status. The occurrence of overvoltage appears in any phase to AC power supply system and it appears in mixing AC and impulse voltages, moreover because HVDC power supply system uses converter in semiconductor, it makes mixed DC and high harmonics voltages. In this study, the various mixed AC and DC voltages was made for investigating the degradation effect of ZnO arrester according to mixed voltage. As a result, the increase of DC component to mixed voltages causes the increase of resistive component of total leakage current to ZnO block. In changing V-I curve for mixed voltages, the cross-over point acts a factor as making the proper capacitor size of an equivalent circuit for ZnO block.

• 정보과학회 컴퓨팅의 실제 논문지
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• 제23권2호
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• pp.134-139
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• 2017

기존의 스크린 미러링 시스템들은 패킷 손실에 취약하며 제한적인 모바일 기기의 에너지를 효율적으로 사용하지 못하는 단점을 가지고 있다. 이를 극복하기 위해 본 연구에서는 패킷 손실에 강인하고 에너지 효율적인 스크린 미러링 시스템을 제안한다. 제안하는 시스템은 패킷 손실로 인한 스크린 미러링 영상의 품질 저하를 완화하기 위해 전방오류정정 기술의 한 종류인 랩터 코드를 적용한다. 그리고 모바일 기기의 효율적인 에너지 사용을 위해 스크린 미러링 데이터에 대한 트래픽 셰이핑을 적용하고, 랩터 인코딩 매개 변수를 조절한다. 제안하는 시스템은 싱글 보드 컴퓨터를 사용하여 실제로 구현 되었으며, WiFi Direct 네트워크 상에서 성능을 검증하였다.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• 한국추진공학회지
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• 제24권2호
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• pp.14-27
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• 2020

본 연구는 점화제와 지연제에 대한 시차 주사 열량 측정법을 통하여 반응 속도식 및 발열량을 추출하여 노화에 따른 반응 특성을 분석하기 위한 정밀 수치계산을 수행하였다. 연소 실험을 수행하여 수분이 관여된 노화에서 점화제와 지연제에서 명확한 연소 중단을 확인하였다. 이 결과를 수치계산과 비교하여 노화가 점화제와 지연제 전반에 성능 감소 및 오작동 요인으로 작용됨을 확인하였다.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• 대한임베디드공학회논문지
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• 제13권3호
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• pp.143-149
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• 2018

It has become ever harder to design reliable circuits with each nanometer technology node; under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Therefore, circuit designers need to consider these reliability effects in the early stages of design to make sure there are enough margins for circuits to function correctly over their entire lifetime. However, such an approach excessively increases the size and power dissipation of a system. As the impact of reliability, new techniques in designing aging-resilient circuits are necessary to reduce the impact of the aging stresses on performance, power, and yield or to predict the failure of a system. Therefore, in this paper, a novel low power on-chip self-tuning circuit considering the aging effects has been proposed.

• Journal of information and communication convergence engineering
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• 제11권4호
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• pp.288-292
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• 2013

In this paper, a carbon implant is investigated in detail from the perspectives of performance advantages and side effects for the thick n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET). Threshold voltage ($V_{th}$) adjustment using a carbon implant significantly improves the $V_{th}$ mismatch performance in a thick (3.3-V) n-MOS transistor. It has been reported that a bad mismatch occurs particularly in the case of 0.11-${\mu}m$ $V_{th}$ node technology. This paper investigates a carbon implant process as a promising candidate for the optimal $V_{th}$ roll-off curve. The carbon implant makes the $V_{th}$ roll-off curve perfectly flat, which is explained in detail. Further, the mechanism of hot carrier injection lifetime degradation by the carbon implant is investigated, and new process integration involving the addition of a nitrogen implant in the lightly doped drain process is offered as its solution. This paper presents the critical side effects, such as Isub increases and device performance shifts caused by the carbon implant and suggests an efficient method to avoid these issues.

• 대한원격탐사학회지
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• 제18권2호
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• pp.91-96
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• 2002

고정 검출 시간(Integration Time)을 갖고 Time Delay and Integration(TDI) Charge Coupled Device (CCD) 검출기를 사용하는 위성 영상 기기에서 위성의 고도 및 촬영각의 변화에 대한 영상 기기의 기하 성능 특성을 TDI 불일치와 관련하여 분석하였다. 본 분석을 통하여 고도 저하에 따른 기하 성능 저하를 보완할 수 있는 방법으로서 경사 촬영을 통한 TDI 불일치 제거를 제안하였고 저하된 고도에서 TDI 일치로 최적 성능을 줄 수 있는 최적 경사 촬영각을 구하였다. 본 결과는 임의의 범위의 가변 검출 시간을 갖는 TDI CCD 위성 영상 기기에도 적용 가능하다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.237.1-237.1
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• 2016

Electrical properties of graphene-based field effect transistors (G-FETs) can be degraded in ambient conditions owing to physisorbed oxygen or water molecules on the graphene surface. Passivation technique is one of a fascinating strategy for fabrication of G-FETs, which allows to sustain electrical properties of graphene in the long term without disrupting its inherent properties: transparency, flexibility and thinness. Ironically, despite its importance in producing high performance graphene devices, this method has been much less studied compared to patterning or device fabrication processes. Here we report a novel surface passivation method by using atomically thin self-assembled alkane layers such as C18- NH2, C18-Br and C36 to prevent unintentional doping effects that can suppress the degradation of electrical properties. In each passivated device, we observe a shift in charge neutral point to near zero gate voltage and it maintains the device performance for 1 year. In addition, the fabricated PG-FETs on a plastic substrate with ion-gel gate dielectrics exhibit not only mechanical flexibility but also long-term stability in ambient conditions. Therefore, we believe that these highly transparent and ultra-thin passivation layers can become a promising candidate in a wide range of graphene based electronic applications.

• Journal of Information Display
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• 제10권3호
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• pp.111-116
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• 2009

In this paper, a plasma-assisted patterning method for the organic layers of organic light-emitting diodes (OLEDs) and its effect on the OLED performances are reported. Oxygen plasma was used to etch the organic layers, using the top electrode consisting of lithium fluoride and aluminum as an etching mask. Although the current flow at low voltages increased for the etched OLEDs, there was no significant degradation of the OLED efficiency and lifetime in comparison with the conventional OLEDs. Therefore, this method can be used to reduce the ohmic voltage drop along the common top electrodes by connecting the top electrode with highly conductive bus lines after the common organic layers on the bus lines are etched by plasma. To further analyze the current increase at low voltages, the plasma patterning effect on the OLED performance was investigated by changing the device sizes, especially in one direction, and by changing the etching depth in the vertical direction of the device. It was found that the current flow increase at low voltages was not proportional to the device sizes, indicating that the current flow increase does not come from the leakage current along the etched sides. In the etching depth experiment, the current flow at low voltages did not increase when the etching process was stopped in the middle of the hole transport layer. This means that the current flow increase at low voltages is closely related to the modification of the hole injection layer, and thus, to the modification of the interface between the hole injection layer and the bottom electrode.