• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국세라믹학회지
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• 제40권2호
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• pp.198-205
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• 2003

R.F. Magnetron Sputtering법을 이용하여 Pt/Ti/ $SiO_2$/Si기판 위에 seed-layers와 $Ba_{0.66}$S $r_{0.34}$Ti $O_3$박막을 제조하였다. 다양한 기판온도에 따른 BST 박막의 전기적인 특성(정전용량과 누설전류)과 seed-layer층이 BST 박막에 미치는 영향을 조사하였다. BST 박막은 seed-layer층을 삽입함으로써 박막의 결정성이 향상되었고, 박막의 기판온도(결정화온도)도 상당히 낮출 수 있었다. 순수한 BST에 비하여 seed-layer를 삽입한 BST는 높은 유전상수와 낮은 유전손실 및 낮은 누설전류를 가지는 우수한 전기적 특성을 나타내었다. BST 박막의 전기적 특성은 기판온도에 따라 영향을 받고, seed-layer에 의해 향상됨을 알 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.365-368
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• 2002

We investigated the influence of RTP annealing of multi-layered metal films deposited on oxides layer. Two types of oxides, BPSG and P-7205, were used as a bottom layer under multi-layered metal film. The bonding was not good in metal/BPSG/Si samples because adhesion between metal layer and BPSG oxide layer was poor by interfacial reaction during RTP annealing above 650$^{\circ}C$. On the other hand bonding was always good in metal/ P-TEOS /Si samples regardless of annealing temperature. We observed the interface between oxide and metal layers using AES and TEM. The phosphorus and oxygen profile in interface between metal and oxide layers were different in metal/BPSG/Si and metal/P-TEOS/Si samples. We have known that the properties of interface was improved in metal/BPSG/Si samples when the sample was annealed below 650$^{\circ}C$.

• 한국재료학회지
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• 제27권8호
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• pp.403-408
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• 2017

We investigated the effect of ZnO buffer layer on the formation of ZnO thin film by ultrasonic assisted spray pyrolysis deposition. ZnO buffer layer was formed by wet solution method, which was repeated several times. Structural and optical properties of the ZnO thin films deposited on the ZnO buffer layers with various cycles and at various temperatures were investigated by field-emission scanning electron microscopy, X-ray diffraction, and photoluminescence spectrum analysis. The structural investigations showed that three-dimensional island shaped ZnO was formed on the bare Si substrate without buffer layers, while two-dimensional ZnO thin film was deposited on the ZnO buffer layers. In addition, structural and optical investigations showed that the crystalline quality of ZnO thin film was improved by introducing the buffer layers. This improvement was attributed to the modulation of the surface energy of the Si surface by the ZnO buffer layer, which finally resulted in a modification of the growth mode from three to two-dimensional.

• 열처리공학회지
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• 제30권4호
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• pp.151-155
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• 2017

The ZTO single layer and ZTO/Ag/ZTO tri-layer films were deposited on glass substrates by using the radio frequency (RF) and direct current (DC) magnetron sputtering and then rapid thermal annealed (RTA) in a low pressure condition for 10 minutes at 150 and $300^{\circ}C$, respectively. As deposited tri-layer films show the 81.7% of visible transmittance and $4.88{\times}10^{-5}{\Omega}cm$ of electrical resistivity, while the films annealed at $300^{\circ}C$ show the increased visible transmittance of 82.8%. The electrical resistivity also decreased as low as $3.64{\times}10^{-5}{\Omega}cm$. From the observed results, it is concluded that rapid thermal annealing (RTA) is an attractive post-deposition process to optimize the opto-elecrtical properties of ZTO/Ag/ZTO tri-layer films for the various display applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.309-310
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• 2006

We studied dielectric properties of OLEDs(Organic Light-emitting Diodes) depending on applied voltage (AC) of PTFE(Polytetrafluoroethylene), material of hole injection layer in structure of ITO/hole injection layer (PTFE)/emitting layer, Alq3(Tris(8-hydroxyquinolibe) Alumin)/Al. PTFE is deposited 2 [nm] as rate of 0.2~03 [${\AA}/s$] and $Alq_3$ is deposited 100 [nm] as rate of 1.3~1.5 [${\AA}/s$] m high vacuum ($5{\times}10^{-6}$[torr]). In result of these studies, we can know dielectric properties of OLEDs. Impedance is decreased depending on applied voltage variation, dielectric loss showed peak in specified voltage and showed cole-cole plot of a specimen.

• 한국전기전자재료학회논문지
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• 제30권7호
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• pp.432-436
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• 2017

IZO transistors with $Al_2O_3$ as gate dielectrics have been investigated. To improve permittivity in an ambient dielectric layer, we grew $Al_2O_3$ by atomic layer deposition directly onto the substrates. Then, we prepared IZO semiconductor solutions with 0.1 M indium nitrate hydrate [$In(NO_3)_3{\cdot}xH_2O$] and 0.1 M zinc acetate dehydrate [$Zn(CH_3COO)_2{\cdot}2H_2O$] as precursor solutions; the IZO solution made with a molar ratio of 7:3 was then prepared. It has been found that these oxide transistors exhibit low operating voltage, good turn-on voltage, and an average field-effect mobility of $0.90cm^2/Vs$ in ambient conditions. Studies of low-voltage driving of IZO transistors with atomic layer-deposited high-k $Al_2O_3$ as gate dielectric provide data of relevance for the potential use of these materials and this technology in transparent display devices and displays.

• 한국진공학회지
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• 제17권3호
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• pp.211-214
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• 2008

Metal organic chemical vapor deposition (MOCVD)를 이용하여 사파이어 기판 위에 405 nm의 파장을 갖는 GaN light-emitting diode (LED)를 제작하였다. LED의 InGaN 활성층에서 생성되어 칩의 후면으로 향하는 광자를 전면으로 반사시키기 위하여, 사파이어 기판 후면에 반사막을 증착하였다. 반사막으로는 Al을 사용하였으며, 사파이어 기판에 대한 Al 박막의 접착력을 개선하기 위하여 사파이어 기판 후면에 Ti를 먼저 증착한 후에 Al을 증착하였다. Ti-Al 반사막을 채용한 결과, 광추출 효율이 52 % 향상되었다.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

• 정보저장시스템학회논문집
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• 제3권4호
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• pp.160-166
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• 2007

In this paper, the measured electrical resistance method is proposed to analyze the ramp-tab contact during the load/unload (L/UL) process. Since this method supplies the voltage change due to the resistance change, we can easily and conveniently identify the ramp-tab contact from the acoustic emission (AE) signal. At first, we carefully deposit the conductive material on the surface of the conventional ramp by sputtering method. The ratio frequency (RF) magnetron co-sputtering system is applied to accomplish the deposited double-layers on the ramp surface. One layer is the stainless steel for the conductive layer and the other is the titanium layer for the cohesive function between the ramp surface and the stainless steel layer. In order to guarantee the stiffness and damping properties of the original ramp, the deposited conductive layer is intended to have very thin thickness. After integration the proposed ramp device into the L/UL system and networking the electrical resistance circuit, the L/UL performance is experimentally evaluated by comparing the measured electrical resistance signal and AE signal.