• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1685-1691
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• 2004

The objective of this study is aimed at reducing the contour error of AC Servo derives by improving the interpolation error of each axis through variable structure control system. The errors in machining process by AC Servo motor are due to many elements, such as the delay of the servo drivers, friction and the gain mismatch between x axis and y axis motors and so on. Sliding mode control system is applied to a AC servo drive as a numerical example in this paper. The experiment results which are compared with those of typical PI scheme show the validity of improvement in circular interpolation error of the system.

• Journal of the Korean Society for Nondestructive Testing
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• v.30 no.6
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• pp.569-577
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• 2010

Nonplanar surface geometries of components are frequently encountered in real ultrasonic inspection situations. Use of rigid array transducers can lead to beam defocusing and reduction of defect image quality due to the mismatch between the planar array and the changing surface. When a flexible array is used to fit the complex surface profile, the locations of array elements should be known to compute the delay time necessary for adaptive heam focusing. An alternative method is to employ the time reversal focusing technique that does not require a prior knowledge about the properties and structures of the specimen and the transducer. In this paper, a time reversal method is applied to simulate beam focusing of flexible arrays and imaging of point-like defects contained in specimens with nonplanar surface geometry. Quantitative comparisons are made for the performance of a number of array techniques in terms of the ability to focus and image three point-like reflectors positioned at regular intervals. The sinusoidal profile array studied here exhibits almost the same image quality as the flat, reference case.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1211-1222
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• 2017

In order to decrease the parameter sensitivity of deadbeat direct torque control (DB-DTC), an improved deadbeat direct torque control method for surface mounted permanent-magnet synchronous motor (SPMSM) drives is proposed. First, the track errors of the stator flux and torque that are caused by model parameter mismatch are analyzed. Then a sliding mode observer is designed, which is able to predict the d-q axis currents of the next control period for one-step delay compensation, and to simultaneously estimate the model parameter disturbance. The estimated disturbance of this observer is used to estimate the stator resistance offline. Then the estimated resistance is required to update the designed sliding-mode observer, which can be used to estimate the inductance and permanent-magnetic flux linkage online. In addition, the flux and torque estimation of the next control period, which is unaffected by the model parameter disturbance, is achieved by using predictive d-q axis currents and estimated parameters. Hence, a low parameter sensitivity DB-DTC method is developed. Simulation and experimental results show the validity of the proposed direct control method.

• Journal of Power Electronics
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• v.16 no.1
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• pp.329-339
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• 2016

Owing to mismatched feeder impedances in an islanded microgrid, the conventional droop control method typically results in errors in reactive power sharing among distributed generation (DG) units. In this study, an improved droop control strategy based on secondary voltage control is proposed to enhance the reactive power sharing accuracy in an islanded microgrid. In a DG local controller, an integral term is introduced into the voltage droop function, in which the voltage compensation signal from the secondary voltage control is utilized as the common reactive power reference for each DG unit. Therefore, accurate reactive power sharing can be realized without any power information exchange among DG units or between DG units and the central controller. Meanwhile, the voltage deviation in the microgrid common bus is removed. Communication in the proposed strategy is simple to implement because the information of the voltage compensation signal is broadcasted from the central controller to each DG unit. The reactive power sharing accuracy is also not sensitive to time-delay mismatch in the communication channels. Simulation and experimental results are provided to validate the effectiveness of the proposed method.

• Journal of Satellite, Information and Communications
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• v.1 no.1
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• pp.54-58
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• 2006

A new design for easily controlling operating frequency of an antenna-integrated planar oscillator is introduced. The oscillator circuit of a broadband negative-resistance active part and a passive load including a patch antenna. The patch resonance is used for determining the oscillation frequency. This design reduces the possibility of mismatch between antenna radiation and oscillation frequencies. To achieve optimum output power, load-pull simulation for the negative-resistance circuit is used. The load-pull simulation shows the feed point and the delay of feed line can affect the oscillation power. Two negative-resistance circuits capable of supporting oscillation over full C-band and X-band are fabricated. The oscillation frequency, output power and phase noise for different patch antennas are measured.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.641-648
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• 2011

Frequency domain equalization is the most promising technology that has relatively low complexity in multipath channel. A frame of single carrier system with frequency domain equalization (SC-FDE) has cyclic prefix to mitigate effect of delay spread. After synchronization and equalization procedure on the SC-FDE system, common phase offset (CPO) that can introduce performance degradation caused by phase mismatch between transmitter and receiver oscillators is remained. In this paper, common phase offset tracking in frequency domain is proposed. To track CPO, constant amplitude zero autocorrelation code sequence as training sequence is adopted. By using numerical results, performance of mean square error is evaluated. The results show that MSE of CPO has similar performance compare to the time-domain estimation and there is no need of domain conversion.