• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.43-52
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• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.50-56
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• 2015

An efficient fast response hysteretic buck converter suitable for mobile application is propoesed. The problems of large output ripple and difficulty in using of small power inductor that conventional hysteretic converter has are improved by adding ramp generator. and the changeable switching frequency with load current is fixed by adding a delay time control circuit composed of PLL structure resulting in decrease of EMI noise. The circuits are implemented by using BCDMOS 0.35um 2-polt 4-metal process. Measurement results show that the converter operates with a switching frequency of 1.85MHz when drives 80mA load current. As the converter drives over 170mA load current, the switching frequency is fixed on 2MHz. The converter has output ripple voltage of less 20mV and more than efficiency 85% with 50~500mA laod current condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1032-1041
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• 2007

The global navigation satellite system (GNSS), which is the core technique for the location based service, adopts the direct sequence/spread spectrum (DS/SS) as its modulation method. The success of a DS/SS system depends on the synchronization between the received and locally generated pseudo noise (PN) signals. As a step in the synchronization process, the tacking scheme performs fine adjustment to bring the phase difference between the two PN signals to zero. The most widely used tracking scheme is the delay locked loop with early minus late discriminator (EL-DLL). In the ideal case, the EL-DLL is the best estimator among various DLL. However, in the band-limited multipath environment, the EL-DLL has tracking bias. In this paper, the timing offset range of correlation function is divided into advanced offset range (AOR) and delayed offset range (DOR) centering around the correct synchronization time point. The tracking bias results from the following two reasons: symmetry distortion between correlation values in AOR and DOR, and mismatch between the time point corresponding to the maximum correlation value and the synchronization time point. The former and latter are named as the type I and type II tracking bias, respectively. In this paper, when the receiver has finite bandwidth in the presence of multipath signals, it is shown that the type II tracking bias becomes a more dominant error factor than the type I tracking bias, and the correlation values in AOR are not almost changed. Exploiting these characteristics, we propose a novel tracking bias mitigation scheme and demonstrate that the tracking accuracy of the proposed scheme is higher than that of the conventional scheme, both in the presence and absence of noise.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.505-511
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• 2008

The global navigation satellite system (GNSS) is using a direct sequence/spread spectrum (DS/SS) modulation. In order to recover the information data, the DS/SS system first performs a two-step synchronization process: acquisition and tracking. The acquisition process adjusts the phase difference between the received and locally generated acquisition sequences within ${\pm}T_c/2$ or less, where $T_c$ is the chip period. The tracking process performs fine synchronization. In this paper, we focus on the tracking issue. The single delta delay locked loop($\Delta$-DLL) is the optimal tracking scheme for a GNSS in the absence of multipath signals, where $\Delta$ means the spacing between the early and late correlation time offset. In the multipath environments, however, the $\Delta$-DLL suffers from huge estimation bias(denoted by $\beta$) caused by distorted correlation values. Although some modified schemes such as a $\Delta$-DLL with a narrow $\Delta$ and a double delta DLL (${\Delta}^{(2)}$-DLL) were proposed to reduce the estimation bias, they cannot remove the estimation bias completely and need more accurate acquisition process. This paper proposes a novel tracking scheme that can dramatically reduce the estimation bias, using the maximum slope change among the correlation outputs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.395-402
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• 2008

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duksty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process and dissipates 184mW at 1.8V single supply The SNDR of the proposed 12bit ADC is 52dB and SFDR of 59dBc(@Fs=20MHz, Fin=1MHz) is measured.