• Title/Summary/Keyword: deglitch

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A 10-Bit 210MHz CMOS D/A Converter (WLAN용 10bit 210MHz CMOS D/A 변환기 설계)

  • Cho, Hyun-Ho;Yoon, Kwang-Sub
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.11
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    • pp.61-66
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    • 2005
  • This paper describes a 10-bit 210MHz CMOS current-mode Digital-to-Analog Converter (DAC) consisting of 6 bit MSB current cell matrix Sub-DAC, 2 bit mSB unary current source Sub-DAC, and 2 bit LSB binary weighting Sub-DAC for Wireless LAN application. A new deglitch circuit is proposed to control a crossing point of signals and minimize a glitch energy. The proposed 10-bit CMOS current mode DAC was designed by a $0.35{\mu}m$ CMOS double-poly four-metal technology rate of 210MHz, DNL/INL of ${\pm}0.7LSB/{\pm}1.1LSB$, a glitch energy of $76pV{\cdot}sec$, a SNR of 50dB, a SFDR of 53dB at 200MHz sampling clock and power dissipation of 83mW at 3.3V

6Bit 2.704Gs/s DAC for DS-CDMA UWB (DS-CDMA UWB를 위한 6Bit 2.704Gs/s DAC)

  • Jung, Jae-Jin;Koo, Ja-Hyun;Lim, Shin-Il;Kim, Suki
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.619-620
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    • 2006
  • This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13um CMOS technology shows s spurious free dynamic range (SFDR) of 50dB from dc to Nyquist frequency. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of $0.76mm^2$.

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A Row Decoder Design and Simulation Considering The Characteristics of PoRAM (PoRAM의 특성을 고려한 행 디코더 설계 및 시뮬레이션)

  • Park, Yu-Jin;Kim, Jung-Ha;Cho, Ja-Young;Lee, Sang-Sun
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.659-660
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    • 2006
  • The low crosstalk row-decoder is studied for PoRAM applications. Because polymer-based memories can be more densely integrated than established silicon-based ones, PoRAM is highly sensitive for the crosstalk problem. To overcome the problem and to suggest the suitable decoder for PoRAM, this paper shows the comparison of the row-path characteristics for both the 2-stage dynamic logic decoder and the 2-stage static logic decoder. Moreover, to suppress the Glitch effect which is observed by using the static logic decoder, the Master-Slave(M/S) D-Flip/Flop(D-F/F) is applied as a deglitch. Finally, the improved output result of the 2-stage static logic decoder with the M/S D-F/F is shown..

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Design of a CMOS D/A Converter for advanced wireless transceiver of high speed and high resolution (고속 고해상도의 무선통신 송 $\cdot$ 수신기용 CMOS D/A 변환기 설계)

  • Cho Hyun-Ho;Park Cheong-Yong;Yune Gun-Shik;Ha Sung-Min;Yoon Kwang-Sub
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.549-552
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    • 2004
  • The thesis describes the design of 12bit digital-to-analog converter (DAC) which shows the conversion rate of 500MHz and the power supply of 3.3V with 0.35${\mu}m$ CMOS 1-poly 4-metal process for advanced wireless transceiver of high speed and high resolution. The proposed DAC employes segmented structure which consists of 6bit MSB, 3bit mSB, 3bit LSB for area efficiency Also, using a optimized aspect ratio of process and new triple diagonal symmetric centroid sequence for high yield and high linearity. The proposed 12bit current mode DAC was employs new deglitch circuit for the decrement of the glitch energy. Simulation results show the conversion rate of 500MHz, and the power dissipation of 85mW at single 3.3V supply voltage. Both DNL and INL are found to be smaller than ${\pm}0.65LSB/{\pm}0.8LSB$.

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Design of Low Power 12Bit 80MHz CMOS D/A Converter using Pseudo-Segmentation Method (슈도-세그멘테이션 기법을 이용한 저 전력 12비트 80MHz CMOS D/A 변환기 설계)

  • Joo, Chan-Yang;Kim, Soo-Jae;Lee, Sang-Min;Kang, Jin-Ku;Yoon, Kwang-Sub
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.13-20
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    • 2008
  • This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.